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1-12 ADSP-21065L SHARC User’s Manual
The Program Sequencer supplies instruction addresses to program mem-
ory. It controls loop iterations and evaluates conditional instructions.
Using an internal loop counter and loop stack, the processor executes
looped code with zero overhead. To loop or to decrement and test the
counter requires no explicit jump instructions.
The processor uses pipelined
fetch
,
decode
, and
execute
cycles to achieve its
fast execution rate. If an application uses external memories, the processor
provides more time to complete an access than accesses requiring no
decode cycle.
The DAGs generate memory addresses when data is transferred between
memory and registers. Dual data address generators enable the processor
to output simultaneous addresses for two operand reads or writes.
DAG1 supplies 32-bit addresses to data memory. DAG2 supplies 24-bit
addresses to program memory for program memory data accesses.
Each DAG keeps track of up to eight address pointers, eight modifiers,
and eight length values. You can modify a pointer used for indirect
addressing with a value in a specified register, either before (premodify) or
after (postmodify) the access. To perform automatic modulo addressing
for circular data buffers, you can associate a length value with each
pointer. And, you can locate circular buffers at arbitrary boundaries in
memory. Each DAG register has an alternate register that you can activate
for fast context switching.
Circular buffers enable efficient implementation of delay lines and other
data structures required in digital signal processing and commonly used in
digital filters and Fourier transforms. The DAG’s automatic handling of
address pointer wraparound reduces overhead, increases performance, and
simplifies implementation.
