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1-16 ADSP-21065L SHARC User’s Manual
an algebraic syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
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The ADSP-21065L contains 544 Kbits of on-chip SRAM, organized into
two banks: Bank 0 has 288 Kbits, and Bank 1 has 256 Kbits. Bank 0 is
configured with 9 columns of 2Kx16 bits, and Bank 1 is configured with 8
columns of 2Kx16 bits. Each memory block is dual-ported for sin-
gle-cycle, independent accesses by the processor’s core and either its I/O
processor or DMA controller. The dual-ported memory and separate
on-chip buses allow two data transfers from the core and one from I/O, all
in a single cycle.
On the ADSP-21065L, the memory can be configured as a maximum of
16K words of 32-bit data, 34K words for 16-bit data, 10K words of 48-bit
instructions (and 40-bit data) or combinations of different word sizes up
to 544 Kbits. All the memory can be accessed as 16-bit, 32-bit, or 48-bit.
The ADSP-21065L supports a 16-bit floating-point storage format, which
effectively doubles the amount of data that it can store on-chip. Conver-
sion between the 32-bit floating-point and 16-bit floating-point formats is
done in a single instruction.
While each memory block can store combinations of code and data,
accesses are most efficient when one block stores data, using the DM bus
for transfers, and the other block stores instructions and data, using the
PM bus for transfers. Using the DM and PM buses in this way, with one
dedicated to each memory block, assures single-cycle execution with two
data transfers, providing the instruction is available in the cache. Sin-
gle-cycle execution is also maintained when one of the data operands is
transferred to or from off-chip, through the ADSP-21065L’s external
port.
