ADSP-21065L SHARC User’s Manual 1-5
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The ADSP-21065L possesses the five central requirements for DSPs estab-
lished in the ADSP-2106x Family of 32-bit floating-point DSPs:
• Fast, flexible arithmetic computation units
• Unconstrained data flow to and from the computation units
• Extended precision and dynamic range in the computation units
• Dual address generators
• Efficient program sequencing
Fast, Flexible Arithmetic
. The ADSP-21065L executes all instructions in
a single cycle. It provides fast cycle times, and, in addition to traditional
multiplication, addition, subtraction, and combined multiplication/addi-
tion, it also provides a complete set of arithmetic operations, including
Seed 1/X, Seed 1
√
X, Min, Max, Clip, Shift, and Rotate. The
ADSP-21065L is IEEE floating-point compatible and supports either
interrupt-on-arithmetic or latched-status exception handling.
Unconstrained Data Flow
. The ADSP-21065L has an enhanced Super
Harvard architecture combined with a 10-port data register file. In every
cycle, the processor can:
• Read or write two operands to or from the Register File,
• Supply two operands to the ALU,
• Supply two operands to the multiplier, and
• Receive two results from the ALU and multiplier.
The processor’s 48-bit orthogonal instruction word supports fully parallel
data transfer and arithmetic operations in the same instruction.
