1-2 ADSP-21065L SHARC User’s Manual
• Host port and multiprocessor interface.
• DMA controller to support ten DMA channels.
• Serial ports with two receivers and two transmitters that support
TDM and I
2
S.
• Two programmable timers and twelve programmable, general-pur-
pose I/O ports.
• JTAG test access port.
Figure 1-1
shows the ADSP-21065L’s Super Harvard Architecture, which
consists of a crossbar bus switch connecting the DSP core’s numeric pro-
cessor to an independent I/O processor, dual-ported memory, and parallel
system bus port.
Figure 1-1. Super Harvard Architecture
Dual-Ported,
Multiaccess
Memory
Numeric
Processor
I/O Processor
&
DMA Controller
Parallel System
Bus Port
Crossbar Bus
Interconnect