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Power Management
Chapter 4
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Preliminary Information
self-refresh mode, and forwards the Stop Grant special cycle
to the PCI bus to the Southbridge.
DRAM refresh must be enabled by writing a 0 to the Ref_Dis test
bit in the DRAM Mode/Status register (Dev 0:F0:0x58, bit 19).
Self-refresh must be enabled by writing a 1 to the Self_Ref_En
bit in the Status/Control register (Dev 0:F0:0x70, bit 18).
DMA cycles initiated from the PCI bus or AGP interface PCI
bus can be probed while in the Stop Grant state during clock
throttling. When a cacheable access is initiated on these
interfaces, the AMD-761 system controller initiates a connect
s e q u e n c e o n t h e A M D A t h l o n s y s t e m b u s v i a t h e
PROCRDY/CONNECT protocol.
Note that when using clock throttling, the Southbridge must be
programmed to wait for the Stop Grant special cycle before
changing the state of the STPCLK# signal.
4.6
DDR DRAM Clock Enables
The AMD-761 system controller is designed to provide BIOS the
ability to disable any unused DDR DRAM clock pairs to reduce
power and system noise. These clock pairs are controlled by the
Clk_Dis[5:0] field in the DRAM Mode/Status register (Dev
0:F0:0x58). The AMD-761 system controller provides six
differential clock pairs to support up to two unbuffered DIMMs or
four registered DIMMs. The usage of these clocks is motherboard-
specific (i.e., which clock pairs connect to which DIMM clock
inputs).
The Clk_Dis bits are initialized to 0 when RESET# is asserted,
thus guaranteeing that all DRAM clock pairs are enabled when
exiting the S3 state.
It is recommended that clock pairs that are connected to
unused DIMM slots be disabled by BIOS. Note that because the
values programmed by BIOS during power-on initialization are
not maintained when entering the S3 state, BIOS is required to
write to the Clk_Dis field when restoring the AMD-761 system
controller configuration registers.
