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Chapter 2

AMD-761™ System Controller  Programmer’s Interface

129

24081D—February 2002 

AMD-761™ System Controller Software/BIOS Design Guide

Preliminary Information

Programming Notes

7–4

IO_Base[15:12]

I/O Base (Write)

The upper writable 4 bits define the bottom address of an address range that is used by
the bridge to determine when to forward I/O transactions from one interface to the other.   

3–0

IO_Base_R

I/O Base (Read)

The lower read-only 4 bits define the bottom address of an address range that is used by
the bridge to determine when to forward I/O transactions from one interface to the other.
0x1 indicates that 32-bit I/O address decoding is available. 

Bit Definitions (Continued)

AGP/PCI Status, I/O Base and Limit (Dev1:0x1C)

Bit

Name

Function

Summary of Contents for AMD-761

Page 1: ...Preliminary Information AMD 761 System Controller Software BIOS Design Guide Publication 24081 Rev D Issue Date February 2002 ...

Page 2: ...oducts including but not limited to the implied warranty of merchantability fitness for a particular purpose or infringement of any intellectual property right AMD s products are not designed intended authorized or warranted for use as components in systems intended for surgical implant into the body or in other applications intended to support or sustain life or in any other applica tion in which...

Page 3: ...2 AMD 761 System Controller Programmer s Interface 9 2 1 Overview 9 2 2 Address Map 10 2 2 1 Special Cycles 12 2 2 2 IACK 15 2 2 3 PCI Configuration Accesses 15 2 3 Address Decoding 16 2 3 1 Socket2000 Address Decoding 16 2 3 2 PCI AGP Master Address Decoding 17 2 4 Configuration Registers 18 2 4 1 I O Register Map 20 2 4 2 Configuration Register Access 26 2 4 3 Device 0 PCI Configuration Register...

Page 4: ...imings 157 3 5 Additional Memory Controller Settings 161 3 6 DRAM Mode Status Settings 165 3 7 ECC and Memory Scrubbing 169 3 7 1 ECC and Memory Scrubbing Configuration 172 3 8 Programmable Delay Lines PDL 174 3 8 1 Manual PDL Window Detection 180 3 9 DDR I O Drive Strength 182 4 Power Management 185 4 1 C1 Halt State Requirements 186 4 2 C2 Stop Grant State Requirements 187 4 3 S1 Power On Suspen...

Page 5: ...2 PCI Chaining 203 5 2 3 PCI Bus Parking 203 6 AGP Interface 205 6 1 AGP Dynamic Compensation Requirements 205 6 1 1 The AGP 4X Dynamic Compensation Register 206 6 1 2 Selection of 1 5 or 3 3 V AGP Signalling 207 6 2 Feature Override Bits for AGP Cards 208 6 3 BIOS Initialization Requirements 209 6 4 AGP Miniport Driver Requirements 210 7 Recommended BIOS Settings 211 7 1 PCI Bus 0 Device 0 Functi...

Page 6: ...6 Table of Contents AMD 761 System Controller Software BIOS Design Guide 24081D February2002 Preliminary Information ...

Page 7: ...AMD Athlon Processor Family Address Mapping 9 Figure 2 AMD Athlon Processor Family x86 Processor Address Mapping 11 Figure 3 AMD 761 System Controller Logical Bus Hierarchy 19 Figure 4 Two Level GART Indexing 139 Figure 5 Suspend to RAM STR_Control Bits Usage 193 Figure 6 Example of System with Flag and Data Stored across PCI Bus Domain 201 ...

Page 8: ...8 List of Figures AMD 761 System Controller Software BIOS Design Guide 24081D February2002 Preliminary Information ...

Page 9: ...le 10 DDR Memory Base Address Register Locations 95 Table 11 AMD 761 DRAM Addressing Modes 96 Table 12 Device 0 Function 1 Configuration Register Map 97 Table 13 PDL Calibration Modes 100 Table 14 DDR PDL Configuration Register Locations 101 Table 15 Device 1 Configuration Register Map 117 Table 16 AMD 761 System Controller Memory Mapped Registers 140 Table 17 Typical CL Parameter Settings for PC1...

Page 10: ...ior with ECC Enabled 171 Table 30 Default DQS Delay versus System Clock Frequency 176 Table 31 AMD 761 System Controller Power Management Features for ACPI Support 186 Table 32 AMD 761 Processor System Controller PCI Read Transaction Options 196 Table 33 Allowable AGP Rate versus Signalling Level 207 Table 34 AGP I O Settings for 1 5 and 3 3 V Signalling 210 ...

Page 11: ...ion 4 on page 185 first Note expanded Section 4 4 on page 190 paragraph two added Section 7 on page 211 paragraph added directly after last bullet in bulleted list The following additional changes were incorporated Table 34 on page 210 values for PSlewXfer and NSlewXfer changed from 01 and 00 respectively to 11 and 11 Updated Revision History 8 2001 C Public release Added bidirectional WSC feature...

Page 12: ...12 Revision History AMD 761 System Controller Software BIOS Design Guide 24081D February2002 Preliminary Information ...

Page 13: ... to properly program the AMD 761 system controller configuration registers The document is organized as follows Section 1 provides an overview of the general BIOS requirements for initializing the AMD 761 system controller configuration registers Section 2 on page 9 contains a description of all AMD 761 system controller configuration registers Section 3 on page 149 contains additional information...

Page 14: ...s mapped in PCI configuration space to device 0 function 1 PCI to PCI bridge AGP registers mapped in PCI configuration space to device 1 function 0 GART Memory Mapped Registers Mapped in memory space as defined by the programming of Base Address 1 GART Memory Mapped Register Base 1 1 2 Special Configuration Sequencing Requirements This section outlines a few cases in the AMD 761 system controller ...

Page 15: ...ed by the AMD 761 system controller AGP miniport driver as memory mapped space This space is defined by the Base Address 1 GART Memory Mapped Register Base Dev 0 F0 0x14 which provides address bits 31 12 of the memory mapped space Note that this space is defined as a 4 Kbyte region hence the lower address bits 11 4 are 0s This register must be properly programmed by BIOS to allow the driver to acc...

Page 16: ...compatibility only Silicon Revisions The reader is advised to read the AMD 761 System Controller Revision Guide order 23613 for the most current information for the version of silicon being used The silicon revision is available by reading the PCI revision ID and Class Code register in Dev 0 F0 0x08 1 1 3 Power On Reset Initialization All of the AMD 761 system controller s configuration registers ...

Page 17: ...54 SBPWaitState 31 Addr_Timing_A 30 Addr_Timing_A 29 RD_Wait_State 28 Reg_DIMM_En 27 tWTR 26 tWR 25 24 tRRD 23 Idle_Cyc_Limit 18 16 PH_Limit 15 14 tRC 11 9 tRP 8 7 tRAS 6 4 tCL 3 2 tRCD 1 0 DRAM Mode Status Dev 0 F0 0x58 Burst_Ref_En 20 Ref_Dis 19 Reserved 18 Cyc_Per_Ref 17 16 CS7_X4Mode 7 CS6_X4Mode 6 CS5_X4Mode 5 CS4_X4Mode 4 CS3_X4Mode 3 CS2_X4Mode 2 CS1_X4Mode 1 CS0_X4Mode 0 Status Control Dev...

Page 18: ...uration Dev 0 F1 0x8C PSlewMDAT 29 27 NSlewMDAT 26 24 PDrvMDAT 19 18 NDrvMDAT 17 16 PSlewDQS 13 11 NSlewDQS 10 8 PDrvDQS 3 2 NDrvDQS 1 0 DDR CLK CS Pad Configuration Dev 0 F1 0x90 PSlewCLK 29 27 NSlewCLK 26 24 PDrvCLK 19 18 NDrvCLK 17 16 PSlewCS 13 11 NSlewCS 10 8 PDrvCS 3 2 NDrvCS 1 0 DDR CMDB CMDA Pad Configuration Dev 0 F1 0x94 PSlewCMDB 29 27 NSlewCMDB 26 24 PDrvCMDB 19 18 NDrvCMDB 17 16 PSlew...

Page 19: ...761 system controller s configuration register when supporting power management Refer to Section 4 on page 185 for further details of these requirements For any system enabling the S3 state a number of core logic PCI configuration registers and processor MSRs must be saved or restored prior to suspending or restoring S3 Also certain hidden bits must be unmasked These requirements apply to all plat...

Page 20: ...ions LockToggle has no function in the AMD 761 system controller 16 ChxToDirtyDis 0 The AMD Athlon processor and the AMD 761 system controller support Change To Dirty commands 13 SysFillValIsD1 0 11 ClVicBlkEn 0 ClVicBlkEn when set causes all evicted clean blocks to cause the CleanVictimBlk system interface command This setting has no function with the AMD 761 system controller 10 8 SetDirtyEnE 0 ...

Page 21: ...view of system memory and peripherals Legacy x86 IBM PC AT memory mappings are implemented by x86 processors AMD Athlon processor as shown in Figure 1 Figure 1 AMD Athlon Processor Family Address Mapping x86 µProcessor Mapping Logic PC Memory View Northbridge Southbridge Socket2000 PCI Alpha µProcessor Conventional View Northbridge Southbridge Socket2000 PCI Memory Same view of the system Processo...

Page 22: ...les generated by the AMD Athlon processor RdBytes commands to this space are used to create PCI IACK The lower 16 bits of these addresses are passed on unmodified to the PCI with the IACK PCI command See Section 2 2 2 on page 15 SysAddOut MSB 0 1 0000 0000 SysAddOut MSB 0 1 F7FF FFFF Reserved Masked May be used by the Northbridge for other purposes used for EV6 Northbridges SysAddOut MSB 0 0 0000 ...

Page 23: ...et2000 memory map is shown in Figure 2 Figure 2 AMD Athlon Processor Family x86 Processor Address Mapping x86 Memory Address Space AGP Virtual PCI Memory Socket2000 Address Space PCI Memory PCI IACK Special PCI I O PCI Config GART DRAM I O Space x86 In and Out Address Space VGA BIOS DOS Memory Extended Memory Reserved Reserved Note Not to scale Reserved TOM CF8 CFC BAR0 APIC Registers 640 1 Mbyte ...

Page 24: ...ut MSB 0 33 0 1 F8000 0000 SysDatOut 31 0 0000 0000 The AMD 761 system controller forwards onto the PCI bus the PCI special cycle command AD 31 0 0000 0000 address and data AMD 766 peripheral bus controllers asserts INIT to processor HALT 0000 0001 The AMD Athlon processor generates in response to executing a HALT instruction WrLWs command SysAddOut MSB 0 33 0 1 F8000 0000 SysDatOut 31 0 0000 0001...

Page 25: ... CONNECT as the first cycle after STOP GRANT or HALT AMD Athlon system bus special cycle regardless of whether or not a disconnect is achieved or even attempted WrLWs command SysAddOut MSB 0 33 0 1 F8000 0000 SysDatOut 31 0 0004 0002 The AMD 761 system controller forwards onto the PCI bus PCI special cycle command AD 31 0 0004 0002 address and data AMD 766 peripheral bus controllers ignores SMM AC...

Page 26: ...roller optionally via Dev0 F0 0x60 on page 61 initiates an AMD Athlon processor system bus disconnect to this specific processor The AMD 761 system controller forwards onto the PCI bus after the optional system bus disconnect PCI special cycle command AD 31 0 0012 0002 address and data The AMD 766 peripheral bus controllers receives and enters the appropriate power state The AMD 766 peripheral bus...

Page 27: ... Data sent during OUT instructions to the Configuration Data register is asserted on the PCI data wires during the generated configuration write transaction Data received in response to a generated configuration read transaction is returned to satisfy the IN from the Configuration Data register In Socket2000 systems PCI configuration cycles are generated in one of two ways In EV6 Compatible mode t...

Page 28: ...en address is to AGP virtual address space and needs to passed through the GART before presentation to DRAM SysAddOut MSB 1 and command is a masked write command WrQWs WrLWs WrBytes DRAM is accessed If SysAddOut 31 0 falls between Dev0 BAR0 and Dev0 BAR0 Len address is to AGP virtual address space and needs to passed through the GART before presentation to DRAM SysAddOut MSB 0 and SysAddOut 35 32 ...

Page 29: ...P PCI Note Low order AMD Athlon processor system bus address bits per the AMD Athlon processor system bus specification SysAddOut only goes down to PA 3 For mask operations the Mask 7 0 bits are encoded to logically create PA 2 0 in the above 2 3 2 PCI AGP Master Address Decoding The PCI controllers in the AMD 761 system controller must consider the received PCI AGP address in conjunction with the...

Page 30: ...ote GART Control register access The AMD 761 system controller does not allow access to the memory mapped GART control registers from either PCI or AGP PCI masters 2 4 Configuration Registers All functional registers in the AMD 761 system controller are implemented as PCI configuration registers The AMD 761 system controller implements a standard PCI hierarchy that allows BIOS software to enumerat...

Page 31: ...er Software BIOS Design Guide Preliminary Information Figure 3 AMD 761 System Controller Logical Bus Hierarchy Processor Host to PCI Bridge PCI to PCI Bridge PCI Devices AGP Master AGP PCI Processor Device 0 F0 F1 PCI to PCI Bridge Device 1 F0 Device 1 F1 Southbridge 2 Processor System Only Future Interface ...

Page 32: ...ccessed by processor I O instructions These registers as presented in Table 5 are the Configuration Address and Configuration Data registers as specified in PCI Local Bus Specification Revision 2 2 Table 5 I O Register Map Register AMD Athlon Processor System Bus Address Reference Configuration Address SysAddOut MSB 0 1 FC000 0CF8 I O 0CF8 on page 21 and I O 0CF8 on page 23 Configuration Data SysA...

Page 33: ...er Description When writes to the configuration address register have 23 16 0h00 a Type 0 configuration access is specified 31 30 29 28 27 26 25 24 Bit Config_En Reserved Reset 0 0 0 0 0 0 0 0 R W R W R 23 22 21 20 19 18 17 16 Bit PCI_Bus_Num Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit Dev_Num Func_Num Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit Reg_Num Reserved Reset 0 0 0 0 0 0...

Page 34: ... in a system by tying the device IDSEL wire to a specific PCI AD wire The AMD 761 system controller decodes this field and asserts the appropriate AD wire during the address phase to select the defined device In the AMD 761 system controller there are two hard wired device numbers for the host to PCI bridge 0b00000 and P2P bridge 0b00001 10 8 Func_Num Function Number This bit field defines which f...

Page 35: ...er Description When writes to the configuration address register have 23 16 0h00 a type 1 configuration access is specified 31 30 29 28 27 26 25 24 Bit Config_En Reserved Reset 0 0 0 0 0 0 0 0 R W R W R 23 22 21 20 19 18 17 16 Bit PCI_Bus_Num Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit Dev_Num Func_Num Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit Reg_Num Reserved Reset 0 0 0 0 0 0...

Page 36: ...bit field defines which PCI bus in the system is referenced with this address The AMD 761 system controller logically implements two PCI buses The main PCI bus normally enumerates as bus 0 and the AGP bus enumerates as bus 1 15 11 Dev_Num Device Number This bit field defines which device is accessed in the system on the target PCI bus This field is passed on directly to the AD wires undecoded 10 8...

Page 37: ...Config_Data Reset x x x x x x x x R W R W 23 22 21 20 19 18 17 16 Bit Config_Data Reset x x x x x x x x R W R W 15 14 13 12 11 10 9 8 Bit Config_Data Reset x x x x x x x x R W R W 7 6 5 4 3 2 1 0 Bit Config_Data Reset x x x x x x x x R W R W Bit Definitions Configuration Data I O 0CFC Bit Name Function 31 0 Config_Data Configuration Data This bit field is used to access the PCI configuration regis...

Page 38: ...I devices must be wired to 1 of AD 31 13 as logically 12 11 are assigned to device 0 1 AMD 761 system controller Function 1 device 0 configuration space contains only the DDR Programmable Delay Line PDL registers This space is enabled only when the appropriate bit is set in the PCI Control register see Dev0 F0 0x4C on page 47 Accesses to the normal reserved PCI space of function 1 yields all 1s Ac...

Page 39: ...de 0x060000 Revision ID 0x08 0x0B Dev0 F0 0x08 on page 35 Reserved Header Type Latency Timer Reserved 0x0C 0x0F Dev0 F0 0x0C on page 36 BAR0 AGP Virtual Address Space 0x10 0x13 Dev0 F0 0x10 on page 37 BAR1 GART Memory Mapped Control Registers Pointer 0x14 0x17 Dev0 F0 0x14 on page 39 Reserved 0x18 0x1B Reserved 0x1C 0x33 Reserved Capabilities Pointer A0 0x34 0x37 Dev0 F0 0x34 on page 41 Reserved 0...

Page 40: ...eserved 0x94 0x97 Reserved 0x98 0x9B PCI Top of Memory Reserved 0x9C 0x9F Dev0 F0 0x9C on page 77 AGP Capability Identifier 0xA0 0xA3 Dev0 F0 0xA0 on page 79 AGP Status 0xA4 0xA7 Dev0 F0 0xA4 on page 80 AGP Command 0xA8 0xAB Dev0 F0 0xA8 on page 82 AGP Virtual Address Space Size 0xAC 0xAF Dev0 F0 0xAC on page 84 GART AGP Mode Control 0xB0 0xB3 Dev0 F0 0xB0 on page 86 AGP 4X Dynamic Compensation 0x...

Page 41: ...emory Base Address 3 0xCC 0xCF Dev0 F0 0xCC on page 95 Memory Base Address 4 0xD0 0xD3 Dev0 F0 0xD0 on page 95 Memory Base Address 5 0xD4 0xD7 Dev0 F0 0xD4 on page 95 Memory Base Address 6 0xD8 0xDB Dev0 F0 0xD8 on page 95 Memory Base Address 7 0xDC 0xDF Dev0 F0 0xDC on page 95 Reserved 0xE0 0xFF Table 6 Device 0 Function 0 Configuration Register Map Continued Host to PCI Bridge Device 0 Function ...

Page 42: ... February2002 Preliminary Information PCI ID Dev0 F0 0x00 Register Description 31 30 29 28 27 26 25 24 Bit Dev_ID Reset 0 1 1 1 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Dev_ID Reset 0 0 0 0 1 1 1 0 R W R 15 14 13 12 11 10 9 8 Bit Vend_ID Reset 0 0 0 1 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Vend_ID Reset 0 0 1 0 0 0 1 0 R W R ...

Page 43: ...tifies the type of device The current Northbridge device ID assignments are AMD 761 system controller AMD Athlon processor 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI to PCI bridge 4 X AGP AMD 762 system controller AMD Athlon processor 2P DDR 133 MHz 0x700C host to PCI bridge 0x700D PCI to PCI bridge 4 X AGP AMD 751 system controller AMD Athlon processor 1P SDRAM 100 0x7006 host to PCI bri...

Page 44: ... 30 29 28 27 26 25 24 Bit PERR_Rcv SERR_Sent Mas_ABRT Trgt_ABRT Trgt_ABRT _ Signaled DEVSEL_Timing Data_PERR Reset 0 0 0 0 0 0 1 0 R W R R W1C R W1C R W1C R R R 23 22 21 20 19 18 17 16 Bit Fast_B2B UDF 66M Cap_Lst Reserved Reset 0 0 0 1 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved FBACK SERR Reset 0 0 0 0 0 0 0 0 R W R R W 7 6 5 4 3 2 1 0 Bit STEP PERR VGA MWINV SCYC MSTR MEM I O Reset 0 0 0 0...

Page 45: ...controller does not terminate transactions with target aborts 26 25 DEVSEL_Timing DEVSEL Timing This bit field defines the timing of DEVSEL on the AMD 761 system controller The AMD 761 system controller supports medium DEVSEL timing 24 Data_PERR Data Parity Error This bit is always 0 because the AMD 761 system controller does not report parity errors 23 Fast B2B Fast Back to Back Capable This bit ...

Page 46: ... SCYC Special Cycle This bit is always 0 because the AMD 761 system controller ignores PCI special cycles 2 MSTR Bus Master Enable This bit is always set indicating that the AMD 761 system controller is allowed to act as a bus master on the PCI bus 1 MEM Memory Access Enable 0 PCI memory accesses ignored 1 PCI memory accesses responded to 0 I O I O Access Enable This bit is always 0 because the AM...

Page 47: ... Bit Class_Code Reset 0 0 0 0 0 1 1 0 R W R 23 22 21 20 19 18 17 16 Bit Sub Class_Code Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Prog_I F Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Rev_ID See Programming Notes below Reset 0 0 0 1 0 0 0 0 R W R Bit Definitions PCI Revision ID and Class Code Dev0 F0 0x08 Bit Name Function 31 24 Class_Code Class Code Indicates a bridge device 23 16 S...

Page 48: ...3 2 1 0 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R Bit Definitions PCI Latency Timer and Header type Dev0 F0 0x0C Bit Name Function 31 24 Reserved Reserved 23 16 Header_Type Header Type Bit 23 is always 0 indicating that the AMD 761 system controller is a single function device Bits 22 16 are 0 indicating that Type 00 configuration space header format is supported 15 8 Lat_Timer Latency Timer This b...

Page 49: ...scription This register is used by system BIOS memory mapping software to allocate virtual address space for AGP 31 30 29 28 27 26 25 24 Bit Base_Addr_High Base Addr_Low Reset 0 0 0 0 0 0 0 0 R W R W R 23 22 21 20 19 18 17 16 Bit Base_Addr_Low Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Base_Addr_Low Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Base_Addr_Low Prefetchable Type Memory R...

Page 50: ...bits 3 1 of that register are set the R W attributes in bits 30 25 in this register are automatically set BIOS software writes all 1s to this BAR register and then reads back the register to determine how much memory is required for AGP as follows 24 4 Base_Addr_Low Base Address Low This bit field is hardwired to return 0s to indicate that the minimum allocated memory size is 32 Mbytes 3 Prefetcha...

Page 51: ... provides the base address for the GART memory mapped configuration register space see Memory Mapped Register Map on page 140 for details 31 30 29 28 27 26 25 24 Bit Base_Addr_High Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit Base_Addr_High Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit Base_Addr_High Base_Addr_Low Reset 0 0 0 0 0 0 0 0 R W R W R 7 6 5 4 3 2 1 0 Bit Base_Addr...

Page 52: ...w Base Address Low This bit field is hardwired to return 0s to indicate that 4 Kbytes are allocated to GART memory mapped control registers and that the registers always reside in a 4 Kbyte boundary per PCI Local Bus Specification Revision 2 2 3 Prefetchable Prefetchable This bit is hardwired to 1 to indicate that this range is prefetchable 2 1 Type Type This bit field is hardwired to indicate tha...

Page 53: ...0 0 0 R W R 7 6 5 4 3 2 1 0 Bit CAP_PTR Reset 1 0 1 0 0 0 0 0 R W R Bit Definitions AGP PCI Capabilities Pointer Dev0 0x34 Bit Name Function 31 8 Reserved Reserved 7 0 CAP_PTR Capabilities Pointer This field contains a byte offset into a device s configuration space containing the first item in the capabilities list The first item in the capabilities list is the AGP function Note that when the AGP...

Page 54: ...controls for the processor interface in addition to the BIU Control register at Dev 0 F0 0x60 for Processor 0 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved Reserved P0_WrDataDly Reset 0 0 0 SIP Stream R W R 7 6 5 4 3 2 1 0 Bit Reserved Reserved Reserved Reserved P0_2BitPF...

Page 55: ...by the processor This value is a calculated part of the SIP stream This value is not provided in the BIU SIP register and is thus provided here 7 4 Reserved Reserved 3 P0_2BitPF Two Bit Times Per Frame Enable This bit enables the use of the two bit time commands on the AMD Athlon processor system bus This bit must be set when connected to an AMD Athlon processor and disabled when connected to an A...

Page 56: ...me bits of this register are not initialized at reset time and all bits must be initialized by BIOS for proper operation This action should be done prior to attempting DRAM access 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit SERR_Enable Reserved ECC_Diag ECC_Mode ECC_Status Reset X X 0 X ...

Page 57: ...to 0x00 For reads the ECC circuitry is unaffected by the ECC_Diag bit The ECC code returned from memory is checked and errors are reported in the ECC_Status bits as usual Correction is not performed in this mode 11 10 ECC_Mode Error Correcting Code Mode 00 ECC disabled no error detection or correction is performed 01 EC_HiPerf mode enabled Error checking and status reporting is enabled Data destin...

Page 58: ...s in this register are not initialized at reset BIOS must initialize all bits in this register prior to attempting DRAM access 7 4 ECC_CS_MED Multiple Bit Error Chip Select These bits provide the binary encoded chip select for the first multiple bit error detected by the AMD 761 system controller 3 0 ECC_CS_SED Single Bit Error Chip Select These bits provide the binary encoded chip select for the ...

Page 59: ...figuration bit is implemented only in Revision B4 silicon and above This bit is reserved and must be cleared in all previous silicon revisions 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved Reserved Reserved Reserved Reset 0 0 0 0 0 0 0 0 R W R R R R 7 6 5 4 3 2 1 0 Bit Reserved Re...

Page 60: ...eet order 24088 for a full description of the WSC pin 0 Bidirectional mode for use with Southbridges that drive WSC as an output and sample WSC as an input such as the AMD 766 peripheral bus controller In this mode the WSC pin of the AMD 761 system controller defaults as an input and is driven by the Northbridge only after the pin is first asserted by the Southbridge 1 Unidirectional mode for use ...

Page 61: ...on Note that the default value of the BYP BYP_P and BYP_N fields of this register can be optionally controlled by SIP bits when loading the SIP stream from external ROM 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit PVal NVal Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit BYP_P BYP_N Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit SlewCntl BYP...

Page 62: ...mpensation circuit In bypass mode bit 4 1 this field returns the values in the BYP_N field bits 11 8 The N values are active High 15 12 BYP_P Bypass Values P Driver Bypass strength values for the P driver The P values are active Low A value of 0 on bit 3 for instance signifies that 2 3 1 or 9 legs of the P driver are active 11 8 BYP_N Bypass Values N Driver Bypass strength values for the N driver ...

Page 63: ... 0x58 on page 57 or attempting any DRAM accesses Note that this register is not initialized at reset time and all bits must be initialized by BIOS for proper operation This action should be done prior to attempting DRAM access 31 30 29 28 27 26 25 24 Bit SBPWaitState AddrTiming_A AddrTiming_B RD_Wait_State Reg_DIMM_En tWTR tWR Reset X X X X X X X X R W R W 23 22 21 20 19 18 17 16 Bit tRRD Reserved...

Page 64: ...determines whether an extra delay is added to the address and command buses MAB 14 0 RASB CASB WEB CKEB CS 7 6 3 2 This bit should be programmed depending on the loading presented to these pins 0 No extra delay 1 XX ps delay 28 RD_Wait_State Read Wait State This bit determines whether a wait state must be added before returning the read data from the memory to the requester This bit should be prog...

Page 65: ...ssive activate commands to different banks 0 tRRD duration is 2 clock cycles 1 tRRD duration is 3 clock cycles 22 19 Reserved Reserved 18 16 Idle_Cyc_Limit Idle Cycle Limit This bit field controls the number of idle cycles to wait before precharging an idle bank Idle cycles are defined as cycles in which no valid requests are asserted 111 Disable idle precharge 110 48 cycles 101 32 cycles 100 24 c...

Page 66: ... This bit field indicates the tRP timing value precharge time time from precharge to activate on the same bank 00 3 cycles recommended safe configuration 01 2 cycles 10 1 cycles 11 4 cycles 6 4 tRAS tRAS This bit field indicates the tRAS timing value minimum bank active time time from activate to precharge of same bank 111 9 cycles 110 8 cycles 101 7 cycles recommended safe configuration 100 6 cyc...

Page 67: ... or attempting DRAM access for correct operation The required settings for the wait state bits for SBP_Wait_State and Rd_Wait_State are listed in Table 8 1 0 tRCD tRCD This bit field tRCD is the timing value RAS to CAS latency delay from activate to RD WR command 11 4 cycles 10 3 cycles recommended safe configuration 01 2 cycles 00 1 cycle Table 8 Wait State Settings for DRAM Timing Register DDR I...

Page 68: ...ialized by BIOS for proper operation This action should be done prior to attempting DRAM access 31 30 29 28 27 26 25 24 Bit Clk_Dis5 Clk_Dis4 Clk_Dis3 Clk_Dis2 Clk_Dis1 Clk_Dis0 SDRAM_Init Reserved Reset 0 0 0 0 0 0 0 0 R W R W R W1S R 23 22 21 20 19 18 17 16 Bit Mode_Reg _ Status STR_Control Burst_Ref_En Ref_Dis Cyc_Per_Ref Reset 0 0 0 X X X X X R W R W1S R W 15 14 13 12 11 10 9 8 Bit Reserved Re...

Page 69: ...0 Clock pair enabled 1 Clock pair disabled three stated Note This bit is meant to disable the clock pair when it is not connected to anything This bit should not be used for memory sizing or power management uses 28 Clk_Dis2 Clock Disable This bit controls the DDR CLKOUT2 CLKOUT2 differential clock pair 0 Clock pair enabled 1 Clock pair disabled three stated Note This bit is meant to disable the c...

Page 70: ... 761 system controller memory controller and power management logic as follows 00 Default These bits are cleared to this state any time the RESET pin is asserted The AMD 761 memory controller always drives the CKE pins inactive Low while these bits are Low 01 BIOS sets this pattern after the system resumes from S4 suspend to disk S5 soft off or mechanical off states This action causes the AMD 761 ...

Page 71: ...sabled 1 This chip select consists of x4 devices enabled 4 CS4_X4Mode Chip Select 4 X4Mode Enable 0 This chip select consists of non x4 devices disabled 1 This chip select consists of x4 devices enabled 3 CS3_X4Mode Chip Select 3 X4Mode Enable 0 This chip select consists of non x4 devices disabled 1 This chip select consists of x4 devices enabled 2 CS2_X4Mode Chip Select 2 X4Mode Enable 0 This chi...

Page 72: ...bits are cleared by RESET and therefore all DDR DRAM interface clock pairs are enabled when exiting the Advanced Configuration and Power Interface ACPI S3 sleep state suspend to RAM BIOS should disable any clock pairs that are connected to unpopulated DIMM slots upon exit of S3 When a chip select is programmed to operate in x4 DIMM mode the DM 8 0 pins become DQS pins for that chip select The pad ...

Page 73: ...on processor system bus interface 31 30 29 28 27 26 25 24 Bit Prb_En Reserved Reserved Reserved Xca_Prb_Cnt Xca_RD_Cnt Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit Xca_RD_Cnt Xca_WR_Cnt Halt_Discon _En Stp_Grant _Discon_En Prb_Limit Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit Prb_Limit Ack_Limit Bypass_En SysDC_Out _Dly Reset 0 0 0 0 1 1 0 Pinstrapping R W R W R R W R 7 6 ...

Page 74: ... field by BIOS software is 0x6 21 19 Xca_WR_Cnt Xca Write Count This bit field represents the maximum number of consecutive AMD Athlon processor system bus grants for write data movement types that are allowed before letting another type have the bus BIOS must program this field to a non zero value for proper operation The recommended value to be loaded in this field by BIOS software is 0x6 18 Hal...

Page 75: ...erved 0b01 1 clock 0b10 2 clocks 0b11 3 clocks This field is initialized by pinstrapping during reset 6 3 SysDC_In_Dly SysDC In Delay This bit field specifies the number of SysClk cycles from a write data type SysDC command and the start of the corresponding data 0b0000 1 clock 0b0001 2 clocks 0b1111 16 clocks This field is initialized by pinstrapping during reset 2 WR2_RD WR2 Read This field defi...

Page 76: ... during the AMD Athlon processor system bus connect protocol 31 30 29 28 27 26 25 24 Bit Clk_Fwd_Offset Data_Init_Cnt Addr_Init_Cnt Sys_Data_Even_Clk_Dly Reset 0 Pinstrapping R W R W R 23 22 21 20 19 18 17 16 Bit Sys_Data_Odd_Clk_Dly Sys_Data_Even_Dly Sys_Data_Odd_Dly Sys_Addr_Dly Reset Pinstrapping R W R 15 14 13 12 11 10 9 8 Bit Sys_Addr_Dly SysDC_Dly Sys_Addr_Clk_Dly Reset Pinstrapping R W R 7 ...

Page 77: ...hases between the nominal start of bit time and the launch of the even data SysData bits 31 16 and 63 48 18 17 Sys_Data_Odd _Dly System Data Odd Delay AMD Athlon processor SIP 25 24 This value specifies the number of processor XICLK phases between the nominal start of bit time and the launch of the odd data SData bits 15 00 and 47 32 16 15 Sys_Addr_Dly System Address Delay AMD Athlon processor SIP...

Page 78: ...in this register is not initialized at reset time but must be initialized by BIOS for proper operation This action should be done prior to attempting DRAM access 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Self_Ref_En Reset 0 0 0 0 0 X 0 0 R W R R W 15 14 13 12 11 10 9 8 Bit Reserved PCI_Pipe_En PCI_Blk_WR _En Reserved Reset 0 0 0 0 0 0 0 0...

Page 79: ... not correctly support the self refresh feature Note that if this bit is not set then DCSTOP assertion ACPI sleep states must be inhibited 0 Self refresh disabled 1 Self refresh enabled 17 14 Reserved 13 Reserved 12 11 Reserved Reserved 10 PCI_Pipe_En PCI Pipe Enable 0 All PCI transactions from either the PCI or AGP interfaces force the memory controller to check for outstanding read probes with a...

Page 80: ... Information Who Am I WHAMI Dev0 F0 0x80 Register Description 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reserved Reserved Reserved BIU0_Present Reset 0 0 0 0 0 0 0 From CPU R W R 15 14 13 12 11 10 9 8 Bit FirstBusID Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit WHAMI Reset CPUID R W R ...

Page 81: ...r is installed on the specified AMD Athlon processor system bus port on the AMD 761 system controller and it has requested a connect sequence ProcRdy assertion 15 8 FirstBusID First BusID This field contains the AMD Athlon processor system bus ID of the first processor to read this register 00h if CPU0 was the first to read WHAMI after reset 01h if CPU1 was the first to read WHAMI after reset 7 0 ...

Page 82: ...4 Bit AGP_VGA_BIOS Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit Tgt_Latency Reserved Reserved AGP_Chain_En PCI_Chain_En Reset 0 0 0 0 0 0 0 0 R W R W R R R W R W 15 14 13 12 11 10 9 8 Bit MDA_Debug PCI_WR_Post _Rtry AGP_WR_Post _Rtry RD_Data_Err _Dis AGP_Erly_Prb _Dis PCI_Erly_Prb _Dis AGP_Arb_Pipe _Dis SB_Lock_Dis Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit PM_Reg_En 15M_Hole 1...

Page 83: ...emory read within 32 clocks for the initial access or 8 clocks for each subsequent access it forces a retry Note To prevent potential deadlocks set this bit and clear bit 3 Tgt_Lat_Tim_Dis if the system has PCI to AGP traffic 22 18 Reserved Reserved 17 AGP_Chain_En Enable AGP Chaining When set CPU writes to the AGP bus are chained together 16 PCI_Chain_En Enable PCI Chaining When set CPU writes to...

Page 84: ...ndard PCI bus 9 AGP_Arb_Pipe_ Dis AGP Arbiter Pipe Disable When set this bit disables the AGP arbiter from pipelining grants onto the bus 8 SB_Lock_Dis Southbridge Lock Disable When the Southbridge makes a request for the PCI bus the AMD 761 system controller makes sure that all the previous posted requests from the processors and PCI are completed by the memory before granting the bus to the Sout...

Page 85: ...t transfer When set this bit disables the AMD 761 system controller s target latency timer on both the standard PCI and AGP PCI interfaces Note To prevent potential deadlocks caused by PCI to AGP traffic on the system this bit should be cleared and bit 23 Tgt_Latency must be set Note also that setting this bit disables the Tgt_Latency function controlled by bit 23 2 AGP_Pref_En AGP Prefetch Enable...

Page 86: ...resh Reset x from PCI AD 14 12 x from PCI AD 7 5 x from PCI AD 20 x from PCI AD 4 R W R 23 22 21 20 19 18 17 16 Bit K7_PP_En IG_PP_En Clk_Speed Reserved S2K0_Bus_Len Reset x from PCI C BE 3 x from PCI C BE 2 x from PCI AD 31 30 x from PCI AD 27 26 x from PCI AD 11 10 R W R 15 14 13 12 11 10 9 8 Bit Tristate_En NAND_En Bypass_PLLs Dis_Divider Reserved Reset x from PCI AD 25 x from PCI AD 23 x from ...

Page 87: ...put thresholds between 1 35 V and 1 9 V When High the inputs sense thresholds between 2 0 V and 2 2 V 23 K7_PP_En AMD Athlon Processor Push Pull Driver Enable When set this bit indicates that the AMD Athlon processor push pull drivers are enabled 22 IG_PP_En AMD 761 System Controller Push Pull Driver Enable When set this bit indicates that the AMD 761 system controller push pull drivers are enable...

Page 88: ...his bit indicates that the AMD 761 system controller delays the INCLK to the AMD Athlon processor When reset the motherboard is expected to provide delay in the etch to center the INCLK with the data 4 Out_Clk_En OUTCLK Enable This bit indicates that the AMD Athlon processor delays the OUTCLK to the AMD 761 system controller When reset the motherboard is expected to provide delay in the etch to ce...

Page 89: ...are the memory addresses of an external PCI master to determine if it is in the range of the AMD 761 system controller DRAM If the address compares then the AMD 761 system controller responds to the bus master access with DEVSEL assertion 31 30 29 28 27 26 25 24 Bit PCI_Mem_Top Reset 1 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit ...

Page 90: ...31 24 PCI_Mem_Top PCI Memory Top This 8 bit field is compared to the incoming PCI bus master address to determine if a memory cycle falls within the AMD 761 system controller DRAM region as follows 31 30 29 28 27 26 25 24 PCIMemTop Field 31 30 29 28 27 26 25 24 PCI Address BIOS should write to this field following completion of the memory sizing algorithm after it has determined the total size of ...

Page 91: ...ointer Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Cap_ID Reset 0 0 0 0 0 0 1 0 R W R Bit Definitions AGP Capability Identifier Dev0 F0 0xA0 Bit Name Function 31 24 Reserved Reserved 23 20 Major_Rev Major Revision Major revision of the AGP interface specification conformed to by this device 19 16 Minor_Rev Minor Revision Minor revision of the AGP interface specification conformed to by this de...

Page 92: ... Information AGP Status Dev0 F0 0xA4 Register Description 31 30 29 28 27 26 25 24 Bit Max_ReqQ_Depth Reset 0 0 0 0 1 1 1 1 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved SBA Reserved Reset 0 0 0 0 0 0 1 0 R W R 7 6 5 4 3 2 1 0 Bit Reserved R4G FW Reserved Rates Reset 0 0 0 0 0 1 1 1 R W R ...

Page 93: ...can be overridden by setting the 4X_Override bit in the AGP 4X Dynamic Compensation register Dev 0 F0 0xB4 bit 6 Bit Definitions AGP Status Dev0 F0 0xA4 Bit Name Function 31 24 Max_ReqQ_ Depth Maximum Command Requests This field contains the maximum number of AGP command requests that this node can manage 23 10 Reserved Reserved 9 SBA Sideband Addressing This field is always 1 indicating that the ...

Page 94: ...ommand Dev0 F0 0xA8 Register Description 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved SBA_En AGP_En Reset 0 0 0 0 0 0 0 0 R W R R W 7 6 5 4 3 2 1 0 Bit Reserved R4G_En Fast_Writes Reserved Data_Transfer_Mode Reset 0 0 0 0 0 0 0 0 R W R R W R R W ...

Page 95: ...en this bit is clear the AMD 761 system controller ignores AGP operations 7 6 Reserved Reserved 5 R4G_En 4GB Address Indicator This bit indicates that the AMD 761 system controller does not support addresses greater than 4 Gbytes The AMD 761 system controller supports only 32 bit addresses 4 Fast_Writes Fast Writes 0 Fast writes disabled 1 Fast writes enabled when the FW_Enable bit is also set in ...

Page 96: ...ation AGP Virtual Address Space Size Dev0 F0 0xAC Register Description 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Vga_IA_En Reset 0 0 0 0 0 0 0 0 R W R R W 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Reserved VA_Size GART_En Reset 0 0 0 0 0 0 0 0 R W R R W ...

Page 97: ...e Changing these bits automatically changes bits 30 25 in the host PCI bridge device 0 AGP Virtual Address Space register offset 0x10 see Dev0 F0 0x10 on page 37 The size of GART virtual address space is always greater than or equal to the amount of physical system memory allocated to AGP in non contiguous 4 Kbyte blocks The amount of physical memory allocated to AGP is determined by operating sys...

Page 98: ...escription This register provides bits to control specific features of the AMD 761 system controller AGP implementation 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved NonGART _Snoop PDC_En Lv1_Index Reset 0 0 0 0 0 0 0 0 R W R R W 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Reserved Reset 0 0 0 0 0 0 0 0 ...

Page 99: ...e processor s When clear AGP addresses that fall outside of the GART range do not cause probes 18 Reserved 17 PDC_En Gart Page Directory Cache Enable This bit is used only in the two level GART mode It has no effect in the one level GART mode The GART directory is enabled only when both this bit and the AGP Features Control register offset 02h of the memory mapped Features and Capabilities registe...

Page 100: ... F0 0xB4 Register Description 31 30 29 28 27 26 25 24 Bit PVal NVal Reset X X X X X X X X R W R 23 22 21 20 19 18 17 16 Bit Reserved DisStrb Quantum_Cnt Reset 0 0 0 0 0 0 0 1 R W R R W R W 15 14 13 12 11 10 9 8 Bit Reserved Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit FW_Enable 4X_Override Comp3 3 Reserved PCI Always_ Compensate Do_ Compensate Reset 0 0 0 0 0 0 0 0 R W R W R R W ...

Page 101: ... and the Fast_Writes enable bit in the AGP Command register Dev 0 F0 0xA8 bit 4 The Fast_Writes status bit in the AGP Status register Dev 0 F0 0xA4 bit 4 is 0 by default indicating that the AMD 761 system controller does not support this feature Setting this bit forces the status bit to a 1 to indicate support of fast writes The fast writes feature is enabled only when this bit and the Fast_Writes...

Page 102: ...When set dynamic compensation is performed by AGP on an ongoing basis at regular intervals 0 Do_Compensate Do Compensate This bit is used to initiate a dynamic compensation command on AGP This bit is cleared by the AMD 761 system controller when the compensation cycle is complete See the programming note below on recommendation for exiting bypass mode Table 9 I O Pad Drive Strength and Input Type ...

Page 103: ...S to bypass the AGP auto compensation to directly control the AGP pad configuration 31 30 29 28 27 26 25 24 Bit BYP_PDrvXfer BYP_NDrvXfer Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit BYPXfer Reserved PSlewXfer NSlewXfer Reset 1 0 0 0 0 0 0 0 R W R W R R W 15 14 13 12 11 10 9 8 Bit BYP_PDrvStrb BYP_NDrvStrb Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit BYPStrb Reserved PSlewStrb NS...

Page 104: ...ield is used to directly program the rise time in all AGP signals except the data strobes This field is not affected by the BYPXfer bit 00 Slew rate 0 slowest 01 Slew rate 1 10 Slew rate 2 11 Slew rate 3 fastest 17 16 NSlewXfer Slew Rate Control This field is used to directly program the fall time in all AGP signals except the data strobes This field is not affected by the BYPXfer bit 00 Slew rate...

Page 105: ...s bypass values are also written 3 2 PSlewStrb Slew Rate Control This field is used to directly program the rise time in all AGP data strobes AD_STB 1 0 AD_STB 1 0 This field is not affected by the BYPStrb bit 00 Slew rate 0 slowest 01 Slew rate 1 10 Slew rate 2 11 Slew rate 3 fastest 1 0 NSlewStrb Slew Rate Control This field is used to directly program the fall time in all AGP data strobes AD_ST...

Page 106: ...g address is parsed to select only one out of the eight chip selects BIOS software is responsible for correctly loading these registers based on data returned from the serial presence detect ROM mechanism through the SMBus implemented in the Southbridge BIOS software must adhere to the following rules when configuring these registers The largest banks are configured first as the lowest addressed m...

Page 107: ...Register 0 Dev0 F0 0xC0 Memory Base Address Register 1 Dev0 F0 0xC4 Memory Base Address Register 2 Dev0 F0 0xC8 Memory Base Address Register 3 Dev0 F0 0xCC Memory Base Address Register 4 Dev0 F0 0xD0 Memory Base Address Register 5 Dev0 F0 0xD4 Memory Base Address Register 6 Dev0 F0 0xD8 Memory Base Address Register 7 Dev0 F0 0xDC 31 30 29 28 27 26 25 24 Bit CS_Base Reset X X X X X X X X R W R W 23...

Page 108: ...ddresses are compared to the CSBase in bits 31 23 above If a given bit is set the corresponding bit in the compare is ignored 6 3 Reserved Reserved 2 1 Addr_Mode Addressing Mode This bit field determines the addressing mode for this CS based on the type of DIMM installed according to Table 11 This addressing applies to the physical addressing on the MAA and MAB address buses Note that modes 00 and...

Page 109: ...age 98 DDR PDL Configuration 0 0x44 to 0x47 Dev0 F1 0x44 on page 101 DDR PDL Configuration 1 0x48 to 0x4B DDR PDL Configuration 2 0x4C to 0x4F DDR PDL Configuration 3 0x50 to 0x53 DDR PDL Configuration 4 0x54 to 0x57 DDR PDL Configuration 5 0x58 to 0x5B DDR PDL Configuration 6 0x5C to 0x5F DDR PDL Configuration 7 0x60 to 0x63 DDR PDL Configuration 8 0x64 to 0x67 DDR PDL Configuration 9 0x68 to 0x6...

Page 110: ...programmable delay lines Note that this register is not initialized at reset time but must be initialized by BIOS for proper operation This action should be done prior to attempting DRAM access 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1...

Page 111: ...the newly written Act_Delay values Software only needs to change the Act_Delay values that are not currently at their desired values the other Act_Dly values are simply re applied This method should be used only when SW_Recal and Auto_Cal_En bits are not set If Auto_Cal_En is set writes to this bit are ignored Also refer to Table 13 PDL Calibration Modes on page 100 This bit always returns a 0 whe...

Page 112: ...fter recomputation is done default 1 Do not update the Actual PDL delay values after recomputation of Cal_Dly is done Note The internal logic tests this bit just prior to updating the Act_Dly so the other bits in this register should be taken into consideration when writing to this bit 3 2 Reserved Reserved 1 0 Auto_Cal_Period Auto Calibration Period This bit field defines how often auto calibrati...

Page 113: ...ter 4 Dev0 F1 0x54 DDR PDL Configuration Register 5 Dev0 F1 0x58 DDR PDL Configuration Register 6 Dev0 F1 0x5C DDR PDL Configuration Register 7 Dev0 F1 0x60 DDR PDL Configuration Register 8 Dev0 F1 0x64 DDR PDL Configuration Register 9 Dev0 F1 0x68 DDR PDL Configuration Register 10 Dev0 F1 0x6C DDR PDL Configuration Register 11 Dev0 F1 0x70 DDR PDL Configuration Register 12 Dev0 F1 0x74 DDR PDL Co...

Page 114: ...s one per DDR DQS pin in x4 mode Note that these registers are not initialized at reset time but must be initialized by BIOS for proper operation This action should be done prior to attempting DRAM access and a software initiated calibration should be forced 31 30 29 28 27 26 25 24 Bit Clk_Dly Reset X X X X X X X X R W R 23 22 21 20 19 18 17 16 Bit SW_Cal_Dly Reset X X X X X X X X R W R W 15 14 13...

Page 115: ...ge of the half period of the system clock and then rounded off to the nearest integer For example if the desired DQS delay is 43 5 percent of the system clock s half period the value written into this field should be 0 434 x 256 111 0x6F Note This bit field should not be used if the system clock frequency is 66 MHz 15 8 Cal_Dly Calibration Delay This bit field provides the last Cal_Dly value in nu...

Page 116: ... register allows BIOS control of the DDR DQS and memory data pad drive strength and slew rate 31 30 29 28 27 26 25 24 Bit Reserved PSlewMDAT NSlewMDAT Reset 0 0 X X X X X X R W R R W 23 22 21 20 19 18 17 16 Bit Reserved PDrvMDAT NDrvMDAT Reset 0 0 0 0 X X X X R W R R W 15 14 13 12 11 10 9 8 Bit Reserved PSlewDQS NSlewDQS Reset 0 0 X X X X X X R W R R W 7 6 5 4 3 2 1 0 Bit Reserved PDrvDQS NDrvDQS ...

Page 117: ...us register Dev 0 F0 0x58 26 24 NSlewMDAT MDAT Falling Edge Slew Rate These bits control the falling edge slew rate of the MDAT 63 0 and DM 8 0 pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest Note that the DM 8 0 pins are controlled by the NSlewDQS field when any chip select is configured for x4 DI...

Page 118: ...ew Rate These bits control the rising edge slew rate of the DQS 8 0 pins and DM 8 0 pins when any chip select is configured for x4 DIMMs in the DRAM Mode Status register at Dev 0 F0 0x58 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 10 8 NSlewDQS DQS Falling Edge Slew Rate These bits control the falli...

Page 119: ...n the DRAM Mode Status register at Dev 0 F0 0x58 00 Drive strength 0 weakest 01 Drive strength 1 10 Drive strength 2 11 Drive strength 3 strongest 1 0 NDrvDQS DQS N Transistor Drive Strength These bits control the N transistor drive strength of the DQS 8 0 pins and DM 8 0 pins when any chip select is configured for x4 DIMMs in the DRAM Mode Status register at Dev 0 F0 0x58 00 Drive strength 0 weak...

Page 120: ...s register allows BIOS control of the DDR clocks and chip selects pad drive strength and slew rate 31 30 29 28 27 26 25 24 Bit Reserved PSlewCLK NSlewCLK Reset 0 0 X X X X X X R W R R W 23 22 21 20 19 18 17 16 Bit Reserved PDrvCLK NDrvCLK Reset 0 0 0 0 X X X X R W R R W 15 14 13 12 11 10 9 8 Bit Reserved PSlewCS NSlewCS Reset 0 0 X X X X X X R W R R W 7 6 5 4 3 2 1 0 Bit Reserved PDrvCS NDrvCS Res...

Page 121: ... Edge Slew Rate These bits control the falling edge slew rate of the CLKOUT 5 0 and CLKOUT 5 0 pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 23 20 Reserved Reserved 19 18 PDrvCLK Clocks P Transistor Drive Strength These bits control the P transistor drive strength of the CLKOUT 5 0 and CLKOUT 5 0...

Page 122: ... slew rate of the CS 7 0 pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 7 4 Reserved Reserved 3 2 PDrvCS CS P Transistor Drive Strength These bits control the P transistor drive strength of the CS 7 0 pins 00 Drive strength 0 weakest 01 Drive strength 1 10 Drive strength 2 11 Drive strength 3 stro...

Page 123: ...lows BIOS control of the DDR RASA RASB CASA CASB WEA WEB CKEA and CKEB pad drive strength and slew rate 31 30 29 28 27 26 25 24 Bit Reserved PSlewCMDB NSlewCMDB Reset 0 0 X X X X X X R W R R W 23 22 21 20 19 18 17 16 Bit Reserved PDrvCMDB NDrvCMDB Reset 0 0 0 0 X X X X R W R R W 15 14 13 12 11 10 9 8 Bit Reserved PSlewCMDA NSlewCMDA Reset 0 0 X X X X X X R W R R W 7 6 5 4 3 2 1 0 Bit Reserved PDrv...

Page 124: ...ling Edge Slew Rate These bits control the falling edge slew rate of the RASB CASB WEB and CKEB pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 23 20 Reserved Reserved 19 18 PDrvCMDB Command B P Transistor Drive Strength These bits control the P transistor drive strength of the RASB CASB WEB and CK...

Page 125: ... RASA CASA WEA and CKEA pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 7 4 Reserved Reserved 3 2 PDrvCMDA Command A P Transistor Drive Strength These bits control the P transistor drive strength of the RASA CASA WEA and CKEA pins 00 Drive strength 0 weakest 01 Drive strength 1 10 Drive strength 2 ...

Page 126: ...register allows BIOS control of the DDR MAA and MAB address bus pad drive strength and slew rate 31 30 29 28 27 26 25 24 Bit Reserved PSlewMAB NSlewMAB Reset 0 0 X X X X X X R W R R W 23 22 21 20 19 18 17 16 Bit Reserved PDrvMAB NDrvMAB Reset 0 0 0 0 X X X X R W R R W 15 14 13 12 11 10 9 8 Bit Reserved PSlewMAA NSlewMAA Reset 0 0 X X X X X X R W R R W 7 6 5 4 3 2 1 0 Bit Reserved PDrvMAA NDrvMAA R...

Page 127: ...ewMAB MAB Falling Edge Slew Rate These bits control the falling edge slew rate of the MAB 14 0 pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 23 20 Reserved Reserved 19 18 PDrvMAB MAB P Transistor Drive Strength These bits control the P transistor drive strength of the MAB 14 0 pins 00 Drive stren...

Page 128: ...ew rate of the MAA 14 0 pins 000 Slew rate 0 slowest 001 Slew rate 1 010 Slew rate 2 011 Slew rate 3 100 Slew rate 4 101 Slew rate 5 110 Slew rate 6 111 Slew rate 7 fastest 7 4 Reserved Reserved 3 2 PDrvMAA MAA P Transistor Drive Strength These bits control the P transistor drive strength of the MAA 14 0 pins 00 Drive strength 0 weakest 01 Drive strength 1 10 Drive strength 2 11 Drive strength 3 s...

Page 129: ...set Reference Device ID Vendor ID 0x00 Dev1 0x00 on page 118 Status Command 0x04 Dev1 0x04 on page 120 Class Code0x0600 Revision ID 0x08 Dev1 0x08 on page 123 Reserved Header Type Primary Latency Timer Reserved 0x0C Dev1 0x0C on page 124 Reserved 0x10 to 0x17 SecLatency Time SubordinateBus Num Secondary Bus Num Primary Bus Num 0x18 Dev1 0x18 on page 125 Secondary Status I O Limit I O Base 0x1C Dev...

Page 130: ... February2002 Preliminary Information AGP PCI ID Dev1 0x00 Register Description 31 30 29 28 27 26 25 24 Bit Dev_ID Reset 0 1 1 1 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit Dev_ID Reset 0 0 0 0 1 1 1 1 R W R 15 14 13 12 11 10 9 8 Bit Vend_ID Reset 0 0 0 1 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Vend_ID Reset 0 0 1 0 0 0 1 0 R W R ...

Page 131: ...entifies the type of device The current Northbridge device ID assignments are AMD 761 system controller AMD Athlon processor 1P DDR 133 MHz 0x700E host to PCI bridge 0x700F PCI to PCI bridge 4X AGP AMD 762 system controller AMD Athlon processor 2P DDR 133 MHz 0x700C host to PCI bridge 0x700D PCI to PCI bridge 4X AGP AMD 751 system controller AMD Athlon processor 1P SDRAM 100 0x7006 host to PCI bri...

Page 132: ...61 system controller This register controls the ability to generate and respond to PCI cycles on both the AGP bus and the PCI bus 31 30 29 28 27 26 25 24 Bit PERR_Rcv SERR_Rcv Mas_ABRT Trgt_ABRT Trgt_ABRTS _Signaled DEVSEL_Timing Data_PERR Reset 0 0 0 0 0 0 1 0 R W R R W1C R 23 22 21 20 19 18 17 16 Bit Fast_B2B UDF 66M Cap_Lst Reserved Reset 0 0 1 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved...

Page 133: ...d is always 0b01 indicating that the AMD 761 system controller supports medium DEVSEL timing 24 Data_PERR Data PERR This bit is always 0 because the AMD 761 system controller does not report data parity errors 23 Fast_B2B Fast Back to Back Capable This bit is always 0 indicating that the AMD 761 system controller as a target is not capable of accepting fast back to back transactions when the trans...

Page 134: ...ntroller does not report data parity errors 5 VGA VGA Palette Snoop Enable This bit is always 0 indicating that the AMD 761 system controller does not snoop the VGA palette address range 4 MWINV Memory Write and Invalidate Enable This bit is always 0 because the AMD 761 system controller does not generate memory write and invalidate commands 3 SCYC Special Cycle This bit is always 0 because the AM...

Page 135: ...8 Bit Prog_I F Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Rev_ID Reset 0 0 0 0 0 0 0 0 R W R Bit Definitions AGP PCI Revision ID and Class Code Dev1 0x08 Bit Name Function 31 24 Class_Code Class Code This field is always 06h indicating that it is a bridge device 23 16 Sub Class_Code Sub Class Code This field is always 04h for sub class code and 00h for Prog I F indicating it is a PCI PCI brid...

Page 136: ... 4 3 2 1 0 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R Bit Definitions AGP PCI Header Type Dev1 0x0C Bit Name Function 31 24 Reserved Reserved 23 16 Header_Type Header Type Bit 23 is always 0 indicating that the AMD 761 system controller is a single function device Bits 22 16 are 0x01 indicating that type 01 configuration space header format is supported PCI to PCI bridge 15 8 Pri_Lat_Timer Primary L...

Page 137: ...tion AGP PCI Sub Bus Number Secondary Latency Timer Dev1 0x18 Register Description 31 30 29 28 27 26 25 24 Bit Secon_Lat_Timer Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit Sub Bus_Num Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit Secon_Bus_Num Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit Pri_Bus_Num Reset 0 0 0 0 0 0 0 0 R W R W ...

Page 138: ... behind or subordinate to a bridge The bridge uses this number in conjunction with the Secondary Bus Number register to determine when to respond to type 1 configuration transactions on the primary interface and to pass them on to the secondary interface 15 8 Secon_Bus_Num Secondary Bus Number This bit field records the number of the PCI bus that the secondary interface of the bridge is connected ...

Page 139: ...determine when to forward I O transactions from one interface to the other The I O Limit register defines the top inclusive of an address range that is used by the bridge to determine when to forward I O transactions from one interface to the other 31 30 29 28 27 26 25 24 Bit PERR_Rcv SERR_Rcv Mas_ABRT Trgt_ABRT Trgt_ABRTS _Signaled DEVSEL_Timing Data_PERR Reset 0 0 0 0 0 0 1 0 R W R R W1C R 23 22...

Page 140: ...VSEL_Timing DEVSEL Timing This field is always 0x1 indicating that the AMD 761 system controller supports medium DEVSEL timing 24 Data_PERR Data PERR This bit is always 0 because the AMD 761 system controller does not report data parity errors 23 Fast_B2B Fast Back to Back Capable This bit is always 0 indicating that the AMD 761 system controller as a target is not capable of accepting fast back t...

Page 141: ...address range that is used by the bridge to determine when to forward I O transactions from one interface to the other 3 0 IO_Base_R I O Base Read The lower read only 4 bits define the bottom address of an address range that is used by the bridge to determine when to forward I O transactions from one interface to the other 0x1 indicates that 32 bit I O address decoding is available Bit Definitions...

Page 142: ...ation AGP PCI Memory Limit and Base Dev1 0x20 Register Description 31 30 29 28 27 26 25 24 Bit MLim 31 20 Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit MLim 31 20 Reserved Reset 0 0 0 0 0 0 0 0 R W R W R 15 14 13 12 11 10 9 8 Bit MBase 31 20 Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit MBase 31 20 Reserved Reset 0 0 0 0 0 0 0 0 R W R W R ...

Page 143: ...registers and FIFO like communication interfaces are mapped The lower 20 bits of address are assumed to be 0xFFFFF The memory address range adheres to 1 Mbyte alignment and granularity 19 16 Reserved Reserved 15 4 MBase 31 20 Memory Base Address Memory Base Address defines the base address of the non prefetchable address range used by the AGP target graphics controller where control registers and ...

Page 144: ...refetchable Memory Limit and Base Dev1 0x24 Register Description 31 30 29 28 27 26 25 24 Bit Prefet_Mem_Lim Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit Prefet_Mem_Lim Reserved Reset 0 0 0 0 0 0 0 0 R W R W R 15 14 13 12 11 10 9 8 Bit Prefet_Mem_Base Reset 0 0 0 0 0 0 0 0 R W R W 7 6 5 4 3 2 1 0 Bit Prefet_Mem_Base Reserved Reset 0 0 0 0 0 0 0 0 R W R W R ...

Page 145: ...where control registers and FIFO like communication interfaces are mapped The lower 20 bits of address are assumed to be 0xFFFFF The memory address range adheres to 1 Mbyte alignment and granularity 19 16 Reserved Reserved 15 4 Prefet_Mem_Base Prefetchable Memory Base Address Prefetchable memory base address defines the base address of the prefetchable address range used by the AGP target graphics...

Page 146: ...es 31 30 29 28 27 26 25 24 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit I O_Lim 23 16 Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit I O_Base 23 16 Reset 0 0 0 0 0 0 0 0 R W R W Bit Definitions AGP PCI I O Limit and Base Upper 16 Bits Dev1 0x30 Bit Name Function 31 24 Reserved Reserved 23 16 I O_Lim 23 16 I O...

Page 147: ... See Note 7 6 5 4 3 2 1 0 Bit Int_Line Reset 0 0 0 0 0 0 0 0 R W R W Bit Definitions AGP PCI Interrupt and Bridge Control Dev1 0x3C Bit Name Function 31 24 Reserved Reserved 23 Bridge_Fast_ B2B_En Fast Back to Back Capable This bit is always 0 indicating that the AMD 761 system controller as a master is not capable of generating fast back to back transactions to different agents on the secondary b...

Page 148: ...sses in the address range defined by the I O Base and I O Limit registers 1 Block forwarding of ISA I O addresses in the address range defined by the I O Base I O Limit registers that are in the first 64 Kbytes of PCI I O address space top 768 bytes of each 1 Kbyte block 17 SERR_En SERR Enable Forwards the secondary interface SERR assertions to the primary interface This bit must be set along with...

Page 149: ...22 21 20 19 18 17 16 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Reserved Int_Pin_Cntl Reset 0 0 0 0 0 0 0 0 R W R R W Bit Definitions Miscellaneous Device 1 Control Dev1 0x40 Bit Name Function 31 1 Reserved Reserved 0 Int_Pin_Cntl Interrupt Pin Control This bit controls the IntPin field in AGP PCI Interrupt and Bridge...

Page 150: ...T cache functionality during run time 2 5 1 AMD 761 System Controller GART Cache Overview This section provides a brief overview for programmers The Graphics Address Relocation Table GART is a structure in memory that contains mappings from a virtual address generated by an AGP master or any other master in the system including PCI masters and the CPU and the actual physical address of a given req...

Page 151: ...liminary Information Figure 4 Two Level GART Indexing Physical Memory GART Directory Directory Entry 1 Directory Entry 2 1K Table Entries 1K Table Entries GART Table Directory Cache Table Cache 16 Entries Fully Associative 8 Entries Fully Associative Northbridge GART Base Address register points here Dev0 BAR1 0x04 AMD 761 System Controller ...

Page 152: ...Initialization Note that BIOS must program the Base Address 1 GART Memory Mapped Register Base register Dev 0 F0 0x14 prior to accessing the memory mapped registers Refer to Dev0 F0 0x14 on page 39 for details of this register Table 16 AMD 761 System Controller Memory Mapped Registers GART Memory Mapped Control Registers Offset from BAR1 Reference Feature Status Feature Control Capabilities Revisi...

Page 153: ...ion 31 30 29 28 27 26 25 24 Bit Reserved Valid_Bit_Err_ID P2P_Status GART_Cache _Status Reserved Valid_Err Reset 0 0 0 0 0 0 0 0 R W R R W1C 23 22 21 20 19 18 17 16 Bit Reserved P2P_En TLB_En SB_STB_Tog _Det Gar_Valid_ Err_En Reset 0 0 0 0 0 0 0 0 R W R R W 15 14 13 12 11 10 9 8 Bit Reserved Hang_En P2P_Cap Link_Cap Valid_Cap Reset 0 0 0 0 0 0 0 1 R W R R W R 7 6 5 4 3 2 1 0 Bit Rev_ID Reset 0 0 0...

Page 154: ...7 on page 34 for details about SERR assertion and status This bit is cleared by writing a 1 23 20 Reserved Reserved 19 P2P_En P2P Enable This bit is hardwired to 0 to indicate that the AMD 761 system controller only implements those PCI to PCI bridge commands required to implement AGP the AMD 761 system controller does not implement a complete PCI 2 1 compliant PCI to PCI bridge between PCI and AG...

Page 155: ... required to implement AGP the AMD 761 system controller does not implement a complete PCI 2 1 compliant PCI to PCI bridge between PCI and AGP 9 Link_Cap LinkCap This bit is always Low indicating that GART entry multiple pages are not supported 8 Valid_Cap ValCap This bit is set to indicate that the AMD 761 system controller supports the detection of valid bit errors 7 0 Rev_ID Revision ID This fi...

Page 156: ...e_Addr Reserved Reset 0 0 0 0 0 0 0 0 R W R W R 7 6 5 4 3 2 1 0 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R Bit Definitions GART Directory Base Address Bar1 0x04 Bit Name Function 31 12 GART_Dir_Base _Addr GART Directory Base Address These bits define the base address of the GART directory that is located in physical system memory These 20 bits correspond to the 20 most significant bits of the 32 bit...

Page 157: ...che_Size Reset 0 0 0 0 0 0 0 0 R W R 23 22 21 20 19 18 17 16 Bit GART_Cache_Size Reset 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit GART_Cache_Size Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit GART_Cache_Size Reset 0 0 0 1 0 0 0 0 R W R Bit Definitions GART Cache Size Bar1 0x08 Bit Name Function 31 0 GART_Cache_Size GART Cache Size The AMD 761 system controller implements a GART table cache ...

Page 158: ... 0 0 0 0 0 0 0 0 R W R 15 14 13 12 11 10 9 8 Bit Reserved Reset 0 0 0 0 0 0 0 0 R W R 7 6 5 4 3 2 1 0 Bit Reserved GART_Cache _Inval Reset 0 0 0 1 0 0 0 0 R W R R W1S Bit Definitions GART Cache Control Bar1 0x0C Bit Name Function 31 1 Reserved Reserved 0 GART_Cache _Inval GART Cache Invalidate This bit is written by the AMD 761 miniport driver When set to 1 the AMD 761 system controller invalidate...

Page 159: ...ription This register must be written to with doubleword 32 bit or 4 byte operands 31 30 29 28 27 26 25 24 Bit GART_Tbl_Entry_Addr Reset 0 0 0 0 0 0 0 0 R W R W 23 22 21 20 19 18 17 16 Bit GART_Tbl_Entry_Addr Reset 0 0 0 0 0 0 0 0 R W R W 15 14 13 12 11 10 9 8 Bit GART_Tbl_Entry_Addr Reserved Reset 0 0 0 0 0 0 0 0 R W R W R 7 6 5 4 3 2 1 0 Bit Reserved Tbl_Update Tbl_Inval _Entry Reset 0 0 0 0 0 0...

Page 160: ...ide of the virtual address space then the invalidate update instructions do nothing 11 2 Reserved Reserved 1 Tbl_Update Table Update When set this bit forces the AMD 761 system controller to update the GART table cache entry specified in bits 31 12 with the current entry in the GART table in system memory The update function is performed immediately following the write to this register When the up...

Page 161: ...page 174 DDR I O Drive Strength on page 182 3 1 Overview To date there are two types of DDR memory DIMMs unbuffered and registered The AMD 761 system controller can be configured to support up to two unbuffered DIMM slots with two banks each or up to four registered DIMM slots with two banks each Registered and unbuffered implementations cannot be intermixed The AMD 761 system controller embeds th...

Page 162: ...The PC1600 naming convention represents DIMMs with a data transfer rate of 1600 Mbytes per second 1 6 Gbytes per second This data rate is calculated as follows PC1600 data transfer rate 100 MHz clock x 2 data transfers clock x 8 bytes transfer PC1600 data transfer rate 1600 Mbytes per second Similarly the PC2100 designation represents DIMMs with a data rate of 2100 Mbytes per second 2 1 Gbytes per...

Page 163: ...ion of this EEPROM is usually provided on a data sheet for the DIMM itself along with data describing the memory devices chips used The data sheet should also contain the byte values for the DIMM encoded in the SPD on the DIMM The SPD is accessed via the I2 C bus implemented on the motherboard normally via registers in a Southbridge agent Subroutines to access SPD data must be provided in the BIOS...

Page 164: ...configuration information for each chip select that is each side of the DIMM These 21 bits are within a full 32 bit configuration register that contains 11 reserved bits Usage of the 32 bits is shown in Table 18 and explained in further detail below As previously mentioned a DIMM socket may be single banked containing one logical side of DDR SDRAM devices or double banked containing two logical si...

Page 165: ...ymmetry of the DDR device that is organization of storage elements rows and columns dictates the addressing mode configuration The specified addressing mode dictates the physical mapping of the memory address signals to the DDR device address signals The addressing modes of the AMD 761 system controller memory controller map to industry standard DDR device symmetries set forth by the Joint Electro...

Page 166: ...e Size of Device value by eight 8 yields the size of the bank in Mbytes If more than 4 Gbytes of total memory are populated in the system it is the responsibility of BIOS to configure and report only 4 Gbytes to prevent a 4 Gbyte wrap which would result in aliasing Table 20 shows the total amount of memory with respect to DDR device density and width Note This table assumes double sided DIMMs Note...

Page 167: ... incoming addresses are compared to the Base Address Chip Select bits Dev 0 F0 0xC0 bits 31 23 through Dev 0 F0 0xDF bits 31 23 defined in Base Address Chip Select If a given bit is set in this register its corresponding address bit in the address compare is ignored Address Mode The Address Mode bits Dev 0 F0 0xC0 bits 2 1 through Dev 0 F0 0xDF bits 2 1 specify the memory address mapping The addre...

Page 168: ... bank For the purpose of illustrating memory sizing the bytes 0xC0 0xDF are the relevant bytes Configuration bytes C0h C1h C2h and C3h are for Bank 0 Byte C0h contains bits 7 0 C1h bits 15 8 etc This example shows 64 Mbytes in both banks 0 Configuration bytes C4h C5h C6h and C7h are for bank 1 Bits C0h 7 and C1h 7 0 contain the Address Mask for 64 Mbytes Bits C4h 7 and C5h 7 0 contain the Address ...

Page 169: ...y will not work Industry standards for CL on DDR DIMMS are 1 5 2 0 and 2 5 Please notice that the AMD 761 system controller supports CL 3 0 as the highest CL setting Some legacy DDR devices support CL 3 0 but most devices available today specify CL 2 5 as a maximum The AMD 761 system controller does not support CL 1 5 3 4 1 Memory Timings The AMD 761 system controller supports the following DDR de...

Page 170: ...3 2 9 Max bus speed for CL 2 5 with AMD 761 system controller 0 DIMM does not support CL 2 5 75h 75h equal 7 5 ns This DIMM can be used CL 2 5 when bus speed is less than or equal to 133 MHz A0h A0h equals 10 ns This DIMM can be used CL 2 5 when bus speed is less than or equal to 100 MHz 23 Max bus speed for CL 2 with AMD 761 system controller 0 DIMM does not support CL 2 75h 75h equal 7 5 ns This...

Page 171: ... and an ACTIVATE command within the same internal bank of the DDR device This timing parameter is DDR device specific Byte 27 of the SPD defines the tRP timing parameter Refer to Table 25 on page 160 for typical settings tRC The Row Cycle time bits Dev 0 F0 0x54 bits 11 9 specify the minimum amount of time that the DDR device requires between ACTIVATE commands within the same internal bank of the ...

Page 172: ... to a following READ command to the same internal bank of the DDR device This device timing parameter is not specified in the SPD but the recommended setting is 1b and specifies two system clock cycles Refer to Table 25 on page 160 for typical settings Table 25 DDR Device Timing Values Symbol Name SPD Byte Typical Value Description tRCD Minimum RAS to CAS Delay 0x0x0x54 1 0 29 50h Has 2 bit fracti...

Page 173: ...e number of consecutive Page Hit requests that are processed by the AMD 761 DRAM controller before choosing a non page hit request This feature is designed to reduce starvation a pending request not fulfilled for an extended period of time due to a flood of consecutive page hit requests Typically consecutive page hits yield the best DDR DRAM page performance for those requesting devices such as th...

Page 174: ...s likely to be accessed again Therefore it is more advantageous to precharge the page and incur the page miss overhead rather than the overhead associated with a page conflict Analysis shows that eight idle clocks is an adequate amount of system clocks to wait for a following request to the memory sub system Therefore these bits should be set to 001b for best performance A higher idle cycle limit ...

Page 175: ...d to a register array that is within the core logic clock domain and physically exists at the pads of the AMD 761 system controller DDR interface When this bit is set to a 1b the data is delayed to the requester by one additional system clock period Because the Read Wait State bit is related to the full read data round trip and may imply that the read data and DQS are being returned from a far DIM...

Page 176: ...D time to the DDR device This bit should be set by BIOS when registered DIMMs are installed and set to 0b when unbuffered DIMMs are installed This bit assumes A bus and B chip select DIMM socket mapping is such that the B bus uses Chip Select bit 5 4 and 1 0 This motherboard mapping should be adhered to should BIOS want to control the A bus and B bus HOLD timing separately Refer to Table 27 on pag...

Page 177: ...between x4 or x8 x16 banks by BIOS setting a corresponding bit for the chip select in this register A bit should be set to 1b to represent a x4 bank or set to 0b to represent a x8 x16 bank The x8 and X16 devices use one DQS data strobe per byte whereas a x4 device uses one DQS data strobe per nibble 4 bit Because the AMD 761 system controller DRAM controller uses the data mask DM signals as DQS da...

Page 178: ...Register Status Dev 0 F0 0x58 bit 23 but only after setting the Mode Register Status bit This procedure is described below The SDRAM Initialization bit is reset to 0b during a Suspend To RAM because a system reset is issued in this case Mode Register Status The Mode Register bit Dev 0 F0 0x58 bit 23 when written with a 1b is used to initiate a Load Mode Register command to the DDR devices The Load...

Page 179: ...emory accesses or interfere with the open page policy by prematurely closing pages due to the refresh When burst refresh is enabled and the burst queue is beginning to fill up the DRAM controller treats the refresh queue requests as an urgent priority Refresh Disable The Refresh Disable bit Dev 0 F0 0x58 bit 19 allows the disabling of refresh cycles for debug purposes only This bit is not reset du...

Page 180: ...d schematic to verify DDR clock DIMM mapping to a particular DIMM slot With a system hard reset these bits are cleared thus enabling all clock pairs Because an AMD 761 system controller system reset is issued during a power managed S3 state all clocks are re enabled following the exit from this state Therefore BIOS should return to this register and restore the disabled clock pairs that it had pre...

Page 181: ... controller DDR SDRAM controller provides five ECC modes All ECC modes work correctly with either unbuffered or registered DDR DIMMs The five modes supported are ECC Disabled High Performance EC Mode EC_HiPerf mode Error Checking only no correction except to the AMD Athlon processor High Performance ECC Mode ECC_HiPerf mode Error Checking and Correction ECC with Scrubbing ECC_Scrub mode Error Chec...

Page 182: ...y locations prior to any ECC function being enabled The additional logic to support the ECC function is costly in both silicon real estate and system timing In the ECC modes that support data correction one additional system clock must be used to generate the corrected data However because the AMD Athlon processor checks for its own errors data is passed directly through the AMD 761 system control...

Page 183: ...C001_0010 15 Table 29 AMD 761 System Controller ECC Behavior with ECC Enabled Operation ECC Generated By ECC Checked By SBEs1 Corrected By AMD Athlon Processor System Bus Read DRAM AMD 761 Sys tem Controller andAMD Athlon Processor AMD Athlon Processor AMD Athlon Processor System Bus Full Quadword Writes AMD Athlon Processor None None AMD Athlon Processor System Bus Partial Quadword Writes AMD 761...

Page 184: ...ue of 0x00 is a valid check bit code so care should be used to not corrupt a location where the user does not expect this valid check bit value to exist In the ECC_Diag mode the AMD 761 system controller always writes 0x00 to the ECC byte to aid testing of the ECC logic For reads the ECC circuitry is unaffected by the ECC_Diag bit The ECC code returned from memory is checked and errors are reporte...

Page 185: ...cessor which performs its own data error detection The AMD 761 system controller provides a high performance ECC mode ECC_HiPerf that provides all the data integrity benefits of ECC but without the overhead of scrubbing In this mode ECC is written into memory during writes partial writes result in a RMW sequence and correction is performed on reads ECC checking is performed and the status indicato...

Page 186: ... when the ECC_Status bits indicate a multi bit error was detected ECC_CS_SED The Single Bit Error Chip Select status provides the binary encoded chip select for the first single bit error detected by the AMD 761 system controller The Failing ECC Chip Select is a binary encoded field and is valid only when the ECC_Status bits indicate a single bit error was detected 3 8 Programmable Delay Lines PDL...

Page 187: ...actual PDL This approach minimizes error between the calibration mechanism and the actual PDLs The range of each PDL is from 1 ns to 2 5 ns worst case The resolution of the PDL is equal to one buffer delay inside the AMD 761 system controller That is the value in the PDL register that controls the tap point of the PDL delay chain represents the number of internal buffer propagation delays Because ...

Page 188: ...surement of how many buffer delays are required to equal the system clock period Because the system clock is generated by a PLL in the AMD 761 system controller and it is already compensated for PVT the system clock period is independent of PVT Therefore the clock period can be assumed to be a constant and can be used to correlate the PDL values Cal_Dly and Act_Dly to units of time Each calibratio...

Page 189: ... self refresh It can either configure the AMD 761 system controller for auto calibration via the Auto_Cal_En bit or it can initiate a single recomputation via the SW_ReCal bit If software initiates a single recomputation via the SW_Recal bit it should also poll for this computation to be done Because auto calibration registers are not initialized at reset it is the responsibility of the BIOS to in...

Page 190: ...Upon exit from self refresh the Act_Dly_Inh bit determines whether the PDLs are updated or not This feature can be useful for diagnostic purposes SW_Recal The Software Re calibration bit Dev 0 F1 0x40 bit 7 provides a way for software to force a re calibration cycle This action is allowed only when the auto calibration feature is disabled A re calibration is forced when this bit is written to a 1b...

Page 191: ...it should not be set if the system clock frequency is 66 MHz Act_Dly_Inh The Actual Delay Update Inhibit bit Dev 0 F1 0x40 bit 4 provides a way for BIOS to inhibit an auto calibration value from updating the PDLs The setting of this bit affects both auto calibration and software initiated calibration but not the Use_Act_Dly method After an exit from self refresh the setting of this bit determines ...

Page 192: ... that is used for the PDL if the Act_Dly_Inh bit Dev 0 F1 0x40 bit 4 is not set If the Act_Dly_Inh bit is set this calculated value is not used to update the PDLs Act_Dly The auto calibrator s Actual Delay Dev 0 F1 0x44 bits 7 0 through Dev 0 F1 0x88 bits 7 0 directly specifies the number of PDL taps BIOS can manually update the PDL by writing a PDL tap value into this register and writing a 1b to...

Page 193: ...r the Actual Delay is configured BIOS must write a 1b to the Use Actual Delay bit Dev 0 F1 0x40 bit 6 to apply the new Actual Delay value Once the operational range for each byte for x8 x16 devices or for each nibble for x4 devices is determined the center point for this window can be determined by dividing these ranges by two which yields the target window PDL tap The average PDL tap value must b...

Page 194: ... calibration system by writing a 1b to Dev 0 F1 0x40 bit 5 3 9 DDR I O Drive Strength The DDR I O pads are SSTL 2 compatible The DDR pads have configurable slew rate and drive strength control of N and P transistors separately It is the responsibility of BIOS to initialize the pad drive strength and slew rate before any memory accesses The DDR I O drive strength and slew controls exist at Dev 0 F1...

Page 195: ...e Chip Select CS 7 0 Command bus A RASA CASA WEA and CKEA Command bus B RASB CASB WEB and CKEB Memory address bus A MAA 14 0 Memory address bus B MAB 14 0 Signal integrity studies have shown that P and N slew settings of 101b and a P drive strength setting of 11b and an N drive strength setting of 10b for all of the signal groups specified above provide adequate edge rates across various unbuffere...

Page 196: ...184 DDR SDRAM Interface Chapter 3 AMD 761 System Controller Software BIOS Design Guide 24081D February2002 Preliminary Information ...

Page 197: ...s are not initialized to a known value at power on with the RESET signal The BIOS must initialize all of these bits for proper operation especially when enabling power management features as described in this section BIOS must also perform a save and restore of all relevant configuration bits in the processor and chipset to support the Suspend to RAM feature Table 31 on page 186 summarizes the var...

Page 198: ...or ACPI Support AMD 761 system controller Power Management Feature ACPI State C1 C2 S1 S3 Disconnect processor when Halt special cycle is detected on AMD Athlon system bus Enabled by BIU Status Control Dev 0 F0 0x60 bit 18 X Disconnect processor when Stop Grant special cycle is detected on AMD Athlon processor system bus Enabled by BIU Status Control Dev 0 F0 0x60 bit 17 for CPU 0 X X X Memory con...

Page 199: ...or s cache causes the AMD 761 system controller to reconnect using the PROCRDY CONNECT protocol There is some additional latency imposed when this mode is enabled because each processor probe requires a reconnect of the CPU When the AMD Athlon system bus is disconnected the processor enters a very low power state The AMD 766 peripheral bus controller Southbridge does not require any special initia...

Page 200: ...e second option requires that the following AMD 761 system controller configuration bits be initialized The Stp_Grant_Discon_En must be set in the BIU Status Control register When this bit is set the AMD 761 system controller flushes internal queues after receiving the Stop Grant special cycle force the DDR DRAM into self refresh mode and forward the Stop Grant special cycle to the PCI bus to the ...

Page 201: ...e PCI bus to the Southbridge DRAM refresh must be enabled by writing a 0 to the Ref_Dis test bit in the DRAM Mode Status register Dev 0 F0 0x58 bit 19 Self refresh must be enabled by writing a 1 to the Self_Ref_En bit in the Status Control register Dev 0 F0 0x70 bit 18 To ensure that no probes are generated all PCI AGP traffic must be prevented by the peripheral software drivers before entering th...

Page 202: ...ered on along with the DRAM and part of the Southbridge while the remaining platform components are powered off For any system enabling the S3 state a number of core logic PCI configuration registers and processor MSRs must be saved or restored prior to suspending or restoring S3 Also certain hidden bits must be unmasked These requirements apply to all platforms regardless of segment and whether o...

Page 203: ... controller configuration registers to a known value when RESET is asserted It is important that these registers be properly initialized by BIOS during the power up configuration Once initialized the AMD 761 system controller retains these values when resuming from the S3 state 4 4 1 STR Bit Control for S3 Support The STR_Control bits are provided to allow BIOS to communicate state changes to the ...

Page 204: ...keup from reset Resume from S3 1X BIOS should write this value to the STR_Control bits when resuming from the S3 Suspend to RAM state This action instructs the AMD 761 system controller memory controller to perform the proper DDR protocol to exit self refresh but not attempt to re initialize the DDR DRAM devices that is mode register writes etc Note that this bit is ignored by the memory controlle...

Page 205: ...AMD 761 system controller flushes internal queues after receiving the Stop Grant special cycle forces the DDR DRAM into STR_Control 00 STR_Control 01 STR_Control 1X Resume from S4 S5 or mechanical off states BIOS writes 01 Resume from S3 state BIOS writes 1X AMD 761 system controller asserts DRAM CKE pins and exits self refresh mode The AMD 761 system controller retains the value of all memory con...

Page 206: ...op Grant special cycle before changing the state of the STPCLK signal 4 6 DDR DRAM Clock Enables The AMD 761 system controller is designed to provide BIOS the ability to disable any unused DDR DRAM clock pairs to reduce power and system noise These clock pairs are controlled by the Clk_Dis 5 0 field in the DRAM Mode Status register Dev 0 F0 0x58 The AMD 761 system controller provides six different...

Page 207: ...tem controller configuration register bits The features and options discussed are as follows PCI delayed transactions and target latency PCI transaction ordering Special arbitration options for Southbridges with legacy DMA requirements Performance enhancement options including read prefetch ing and PCI chaining 5 1 Delayed Transactions and Ordering Rules Usage The AMD 761 system controller provide...

Page 208: ... the next read cycle falls within the maximum target latency Setting the delayed transaction enable PCI_DT_En causes the AMD 761 system controller to latch the address and read command that was initiated by the external master Table 32 AMD 761 Processor System Controller PCI Read Transaction Options PCI_DT_En Dev 0 F0 0x4C bit 2 PCI_OR_En Dev 0 F0 0x4C bit 1 Tgt_Latency Dev 0 F0 0x84 bit 23 Descri...

Page 209: ...e time that the memory subsystem is retrieving the read data for peer to peer PCI traffic between other PCI masters and agents Unfortunately this type of traffic is rare in most systems It should be noted that the AMD 761 system controller supports only a single level delayed transaction queue thus the performance benefit may be minimal and may actually be worse with delayed transactions enabled u...

Page 210: ...d the address and initiates a memory read to the memory controller and simultaneously issues a probe to the processor The memory subsystem is unable to return the data within 32 PCI clocks so it asserts the STOP signal while TRDY remains inactive This action causes the master that originated the cycle to disconnect and it must re arbitrate for the bus Meanwhile the AMD 761 system controller memory...

Page 211: ... the flushing of posted write FIFOs in the AMD 761 system controller Figure 6 on page 201 illustrates an example system implementation with data and associated flags stored in different locations In this example the flag is stored in main memory DRAM and the data is stored in the PCI agent The sections that follow describe the behavior in a system with and without ordering rules compliance With Or...

Page 212: ...roller when ordering rules are not followed 1 The processor writes data memory write destined to an agent on the PCI bus and the data is posted in the AMD 761 system controller PCI posting buffer 2 The processor then sets a flag in memory informing the PCI agent that the data is written 3 The PCI master reads the flag but the associated data previously written by the processor has not been flushed...

Page 213: ... the PCI bus as a master This design prevents potential deadlock conditions that can occur with legacy DMA There are no BIOS requirements to enable or disable this functionality Before winning bus arbitration the AMD 761 system controller s internal memory read and write queues can optionally be locked and flushed This option is controlled by the SB_Lock_Dis bit in the PCI Arbitration Control regi...

Page 214: ...ad Prefetching When the AMD 761 system controller is the target of PCI memory read accesses to system memory the AMD 761 system controller s PCI target interface initiates a probe of the AMD Athlon processor s cache and a read of eight quadwords a single cache line from memory Setting the read prefetching bit PCI_Pref_En Dev 0 F0 0x84 bit 1 causes the AMD 761 system controller to prefetch another ...

Page 215: ... set for optimal performance 5 2 3 PCI Bus Parking The PCI Local Bus Specification Revision 2 2 requires that a default bus owner be designated that always drives the bus to a known value to prevent the bus from floating for long idle periods The AMD 761 system controller provides two options for bus parking Park on the AMD 761 system controller that is CPU accesses to PCI agents Park on the last ...

Page 216: ...204 PCI Bus Interface Chapter 5 AMD 761 System Controller Software BIOS Design Guide 24081D February2002 Preliminary Information ...

Page 217: ... described in this section Two separate 32 bit configuration registers are used to control AGP I O characteristics 1 AGP Dynamic Compensation register Dev 0 F0 0xB4 2 AGP Compensation Bypass register Dev 0 F0 0xB8 Two modes are provided in the AGP compensation circuitry Automatically compensate once or at regular intervals by adjusting the drive strengths of the AGP interface I O cells In this cas...

Page 218: ...es read back allow BIOS to determine if the correct compensation resistors are installed on the motherboard Quantum_Cnt Always_Compensate These fields are used to enable 1 5 V signalling compensation at regular intervals which is the suggested method for all 4X AGP non strobe signals The Quantum_Cnt field can be programmed for the maximum value 6 4 seconds because it is not expected that a more fr...

Page 219: ...us 3 3 V is done by the AGP card via the TYPEDET pin when it is installed in the AGP slot AGP cards operating in 3 3 V signalling mode have their TYPDET pin unconnected Cards operating in 1 5 V signalling mode have the pin connected to VSS forcing it to 0 The AMD 761 system controller latches the value of the TYPEDET pin at reset and BIOS can read this value in the Configuration Status register De...

Page 220: ...AMD 761 system controller into 4X mode but this speed is not supported when 3 3 V signalling is selected The solution is for the AMD 761 system controller to report capability of a maximum of 2X AGP speed in this configuration The two override bits are described below and specific programming recommendations are listed in Section 6 3 4X_Override This bit is used to force the 4X rate bit to 0 in th...

Page 221: ...then 1 5 V signalling is selected by the AGP card If 1 then 3 3 V signalling is used 2 Configure the override bits according to the signalling level as listed in Table 34 on page 210 and the following notes If 1 5 V then the 4X_Override bit should be cleared and the FW_Enable bit should be set in the AGP 4X Dynamic Compensation register Dev 0 F0 0xB4 bits 6 and 7 respectively This action causes th...

Page 222: ...and device ID in PCI configuration space AMD does not plan for any current or future generation AGP cards to experience any incompatibilities with the AMD 761 system controller If a card is identified that requires a drive strength change the AMD mini port or the AGP card is updated to allow compatibility Table 34 AGP I O Settings for 1 5 and 3 3 V Signalling Register Bit Field Name Bits 1 5 V Val...

Page 223: ... set or controlled by BIOS This is mandatory No setting can be assumed by default Refer to the actual configuration register descriptions for details of each bit These can be found in AMD 761 System Controller Programmer s Interface on page 9 of this document The final and precise definition of bits in the SPD of a DDR DIMM can be found in JEDEC reference materials and specifications Values that a...

Page 224: ... are mostly specific to the AMD 761 system controller and its processor DDR SDRAM AGP and PCI bus interfaces The Bus 0 Device 0 space contains two separate functions as follows Function 0 contains standard PCI configuration space timing and arbitration control for each interface and memory decode registers Function 1 contains DDR drive strength control and calibration control for the programmable ...

Page 225: ...g 01b r 24 Data_PERR 0b r 23 FastB2B 0b r 22 UDF 0b r 21 66M 0b r 20 Cap_Lst 1b r 19 10 Reserved 000h r 9 FBACK 0b 8 SERR System Error Enable yb u 0 Disable 1 Enable 7 Step 0b r 6 PERR 0b r 5 VGA Palette Snoop 0b r 4 MWINV 0b r 3 SCYC 0b r 2 MSTR 1b r 1 MEM 1b B PCI memory access enable 0 IO 0b r IO access disable on PCI bus 0x0x0x08h PCI Rev ID and Class Code 31 24 Class Code 06h r Bridge device ...

Page 226: ... specification 2 1 BAR0 Type mem as 32 bits 00b r PCI specification 0 Flags BAR0 as MEMORY Address Space 0b r PCI specification 0x0x0x14h BAR1 GART Memory Mapped Register Base 31 12 GART Memory Mapped Base Address Register Settable portion of Address xxxx_xh A 11 4 GART Memory Mapped Base Address Register Low hardwired to force 4 Kbytes 00h r 3 BAR1 mem Prefetchable 1b r PCI specification 2 1 BAR1...

Page 227: ... r 15 14 SERR_Enable xxb B 00b ECC SERR Disabled 1xb SERR on Multi_Bit Errors x1b SERR on Single Bit Errors See SERR 0x0x0x4 8 13 Reserved 0b r 12 ECC_Diag 0b B 0 Disable 1 Enable 11 10 ECC_Mode SPD 11 xxb B SPD 00b NO ECCorECCDisabled 01b Data Errors Reported 10b Data Errors Corrected for Memory and PCI AGP 11b Data Errors Corrected and Memory Scrubbed 9 8 ECC_Status 00b B 00b No Error x1b MED Mu...

Page 228: ...es Compliance 0 Func1_En 0b B 1 Enable 0x0x1xRR Access 0x0x0x50h AMD Athlon System Bus Dynamic Compensation 31 24 Reserved 00h r 23 20 PVal yh c P Transistor Value in Use 19 16 NVal yh c N Transistor Value in Use 15 12 Byp_P 0h B P Transistor Value Used if Byp 1 11 8 Byp_N 0h B N Transistor Value Used if Byp 1 7 5 SlewCntl 011b B 4 Byp 0b B 1 Enable Byp_P and Byp_N 3 0 Reserved 0h r KEY B Mandator...

Page 229: ...ve BankCommandDelay SPD 28 xb B SPD 0 2 Clocks 1 3 Clocks 22 19 Reserved 000_0b r 18 16 Idle cycle to wait before pre charging the idle bank Include bit 24 above 001b B 000 0 cyc 001 8 cyc safe 010 12 cyc 011 16 cyc 100 24 cyc 101 32 cyc 110 48 cyc 111 Disable 15 14 Page Hit request before a nonPage hit 10b B 00 1 cyc 01 4 cyc 10 8 cyc safe 11 16 cyc 13 12 Reserved 00b r 11 9 tRC Bank Cycle Time t...

Page 230: ... Description Initialized Required Value Actual Value Key fcn Notes 0x0x0x54h SDRAM Timing 6 4 tRAS Minimum Bank Active Time SPD 30 xxxb B FSB and SPD 000 2 cyc 001 3 cyc 010 4 cyc 011 5 cyc 100 6 cyc 101 7 cyc safe 110 8 cyc 111 9 cyc 3 2 tCL CAS Latency SPD 25 or 23 or 9 xxb B FSB and SPD 00 3 cyc optional on DIMM not recommended 01 2 cyc recommended 10 2 5 cyc 11 reserved 1 0 tRCD RAS to CAS Lat...

Page 231: ...001b 000 0 cyc 001 8 cyc safe 010 12 cyc 011 16 cyc 100 24 cyc 101 32 cyc 110 48 cyc 111 Disable 15 14 Page Hit request before a nonPage hit 10b 10b 00 1 cyc 01 4 cyc 10 8 cyc safe 11 16 cyc 13 12 00b 00b 11 9 tRC Bank Cycle Time tRAS tRP or SPD 41 new not yet implemented 100b 110b to 111b 41h to 46h 65 to 70 000 3 cyc 001 4 cyc 010 5 cyc 011 6 cyc 100 7 cyc 101 8 cyc safe 110 9 cyc 111 10 cyc 8 7...

Page 232: ...register status xb B To be set before or with SDRAM Init Causes writing of the memory mode register when SDRAM Init is set After setting drops to 0 when function complete Cannot be set to 0 22 21 STR_Control Suspend to RAM Control xxb B Set Last Power State 01b MOFF S4 or S5 10b S3 Refer to S3 Suspend to RAM State Requirements on page 190 for details 20 Burst refresh enable 0b B 0 Disable 1 Enable...

Page 233: ...4_X4Mode Chip Select x4 Enable SPD 13 xb B SPD 0 x8 x16 1 x4 DIMM devices 3 CS3_X4Mode Chip Select x4 Enable SPD 13 xb B SPD 0 x8 x16 1 x4 DIMM devices 2 CS2_X4Mode Chip Select x4 Enable SPD 13 xb B SPD 0 x8 x16 1 x4 DIMM devices 1 CS1_X4Mode Chip Select x4 Enable SPD 13 xb B SPD 0 x8 x16 1 x4 DIMM devices 0 CS0_X4Mode Chip Select x4 Enable SPD 13 xb B SPD 0 x8 x16 1 x4 DIMM devices KEY B Mandator...

Page 234: ... page 185 for details 16 14 Probe limit 110b B 0 7 1 to 8 probes 110b 7 recommended 13 10 Ack limit 0000 1 un acked command 0001 2 0011b r This field should be used to set up SysAckLimit in AMD Athlon 1 to this value SYSCFG 9 Bypass_ En Super Bypass Enable 1b B 0 Disable 1 Enable 8 7 SysDC_Out_ delay yyb r From init logic 6 3 SysDC_In_ delay yyyyb r From init logic 2 WR2_RD yb r From init logic 1 ...

Page 235: ...fore PCI transactions 1 MRO pipelines PCI transactions 9 PCI Block Write Enable 1b B 0 BIU does RID INV probes forcing MRO MWQ to wait for data movement 1 BIUdoesNOP INVprobes for PCI full block writes 8 0 Reserved 000h B 0X0X0X80h Who AM I 31 17 Reserved 00b 000h r 16 BIU0 present 1b c 15 8 First AMD Athlon system bus ID 00h c 7 0 Who AM I 00h c KEY B Mandatory BIOS function A AGP setup by BIOS c...

Page 236: ...es to AGP are chained 16 PCI Chaining 1b B Enabled 1 when set CPU writes to PCI are chained 15 MDA Support 0b A Enabled 1 allows monochrome adapter for AGP device driver debug Normally 0 See AMD 761 System Controller Data Sheet order 24088 for information 14 PCI Write Post retry 1b B 1 Enables retry on PCI if there are pending posted writes 13 AGP Write Post retry 1b B 1 Enables retry on AGP if th...

Page 237: ...le xb B 1 Enable a memory hole at 14 15 MBytes 4 EV6 mode 1b B 1 Enable PCI decoding in EV6 mode Used for opening buffers in 640K to 1 Mbyte memory address space Legacy USB SCSI devices sometimes need this capability 3 Target latency timer disable 1b B 0x0x 0x84 23 1 Disable AMD 751 system controller target latency timer on both PCI and AGP s PCI interfaces 2 ApcPreEn 0b B 1 Disables AMD 751 syste...

Page 238: ... MHz 10b Reserved 11b 133 MHz 19 18 Reserved yyb r 17 16 S2K_Bus_Len yyb r 15 Tristate_En yb r 14 Nand_En yb r 13 Bypass_PLLs yb r 12 Dis_Divider yb r 11 8 Reserved yh r 7 Sip_ROM yb r 6 Reg_DIMM_En yb r 0 Unbuffered 1 Registered 5 In_Clk_En yb r 4 Out_Clk_En yb r 3 0 CPU0_Divider yh r 0x0x0x9Ch PCI Top of Memory 31 24 PCI Memory Top xxh B Actual Memory Size AD 31 24 23 0 Reserved 000_0000h r KEY ...

Page 239: ...port 0 Fast Write Not Supported 3 Reserved 0b r 2 0 Rates 111b r AMD 761 system controller supports 1x 2x 4x 0x0x0xA8h AGP Command Register 31 10 Reserved 0000_0h 00b r 9 SBA_Ena Sideband addressing enable yb o Set by operating system agent not BIOS 0 Disable 1 Enable 8 AGP_Ena AGP operation enable yb o Set by operating system agent not BIOS 0 Disable 1 Enable 7 6 Reserved 0b r 5 Greater than 4G a...

Page 240: ...2 Gbytes 128 Mbytes recommended 0 GARTEna AGPaperture base address enable xb A 0 Disable register 1 Enable register 0 0x10 BAR0 and start GART 0x0x0xB0h Gart AGP Mode Control 31 21 Reserved 00h 000b r 20 Reserved 0b B 19 NonGART Snoop 0b B Debug Performance register 0 Disable probes 1 Enable probes 18 Reserved 0b B 17 GART page directory cacheenable 0b B Debug Performance register 0 Disable 1 Enab...

Page 241: ...Feature Override Bits for AGP Cards on page 208 for details 6 4x_Override xb A B4 BF 0 Disabled 1 Enabled Forces 0x0x0xA4h 0 010b 2x AGP Refer to Feature Override Bits for AGP Cards on page 208 for details 5 Comp3 3 0b A Do_Compensate 1 shows PValandNValwhenComp3 3 1 with 3 3 V AGP cards 4 3 Reserved 0b r 2 PCI drive strength 0b A Normally 0 1 Always_Compensate xb A B4 BB 0 Disable 1 Enable Refer ...

Page 242: ... fordetails 22 20 Reserved 000b r 19 18 BYP_PSlewXfer xxb A B4 BB P slew rate value for data Referto BIOS Initialization Requirements on page 209 fordetails 17 16 BYP_NSlewXfer xxb A B4 BB N slew rate value for data Referto BIOS Initialization Requirements on page 209 fordetails 15 12 BYP_PDrvStrb xh A B4 BB P drive bypass value for strobes Referto BIOS Initialization Requirements on page 209 ford...

Page 243: ...4 Reserved 000b r 3 2 BYP_PSlewStrb xxb A B4 BB P slew rate value for strobes Refer to BIOS Initialization Requirements on page 209 for details 1 0 BYP_NSlewStrb xxb A B4 BB N slew rate value for strobes Refer to BIOS Initialization Requirements on page 209 for details KEY B Mandatory BIOS function A AGP setup by BIOS c Calculated set by AMD 761 internal logic P Power management setup by BIOS o Se...

Page 244: ...ypass register Type_Det 1 2X AGP Maximum Type_Det 1 3 3 V card in AGP slot 0x0x0x B4h B5h B6h B7h B8h B9h BAh BBh No Option 48h 00h 01h C5h 0Fh FFh 0Fh C5h Type_Det 0 4X AGP Maximum Reduced to 2X AGP with 4X_Override 0x0x0x B4h B5h B6h B7h B8h B9h BAh BBh Option 1 4Ah 00h 01h D8h 8Fh FFh 04h D8h 4x_OverrideandAlways_Compensate 0x0x0x B4h B5h B6h B7h B8h B9h BAh BBh Option 2 48h 00h 01h D8h 8Fh FFh...

Page 245: ...0011_1b 64 Mbytes 0000_0111_1b 128 Mbytes 0000_1111_1b 256 Mbytes 0001_1111_1b 512 Mbytes 0011_1111_1b 1 Gbyte 0111_1111_1b 1 Gbyte 6 3 Reserved 0h r 2 1 Addr_Mode SizeofDevice SizeofBankx Primary SDRAM Width 8 xxb B SPD 31 and 13 01b SDRAM device 256 Mbits 10b SDRAM device 128 Mbits 00b and 11b are reserved 0 Enable Disable Bank 1 xb B 0 Disable CS 1 Enable CS 0x0x0xC4h Memory Base Address Regist...

Page 246: ... xb B As 0x0x0xC0h above 22 16 Reserved 000b 0h r As 0x0x0xC0h above 15 7 Chip Select Mask 2 xxh xb B As 0x0x0xC0h above 6 3 Reserved 0h r As 0x0x0xC0h above 2 1 Addr_Mode xxb B As 0x0x0xC0h above 0 Enable Disable Bank 2 xb B As 0x0x0xC0h above 0x0x0xCCh Memory Base Address Register 3 31 23 Chip Select Base 3 xxh xb B As 0x0x0xC0h above 22 16 Reserved 000b 0h r As 0x0x0xC0h above 15 7 Chip Select ...

Page 247: ... xxb B As 0x0x0xC0h above 0 Enable Disable Bank 5 xb B As 0x0x0xC0h above 0x0x0xD8h Memory Base Address Register 6 31 23 Chip Select Base 6 xxh xb B As 0x0x0xC0h above 22 16 Reserved 000b 0h r As 0x0x0xC0h above 15 7 Chip Select Mask 6 xxh xb B As 0x0x0xC0h above 6 3 Reserved 0h r As 0x0x0xC0h above 2 1 Addr_Mode xxb B As 0x0x0xC0h above 0 Enable Disable Bank 6 xb B As 0x0x0xC0h above 0x0x0xDCh Me...

Page 248: ... strengths and calibration of the Programmable Delay Lines PDLs All Function 1 register bits are defaulted to an unknown value as required for the AMD 761 system controller to support the Advanced Configuration and Power Interface ACPI S3 Suspend to RAM state For proper operation it is absolutely necessary that BIOS initialize all Function 1 register bits Please obtain the AMD 761 System Controlle...

Page 249: ...B2 silicon 4 Act_Dly_Inh Actual Delay Update Inhibit 0b B 0 Disable 1 Enable Refer to AMD 761 System Controller Revision Guide order 23613 for special instructions for Revision B2 silicon 3 2 Reserved 00b r 1 0 Auto_Cal_Period Auto Calibration Period 01b B 00 10000 System Clocks 01 1000000 System Clocks 10 10000000 System Clocks 11 Reserved 0x0x1x44h DDR PDL Configuration Register 0 31 24 Clk_Dly ...

Page 250: ..._Dly yyh c Half Period of the System Clock 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers 7 0 Act_Dly xxh c fromSW_RecalorDirectWrite 0x0x1x54h DDR PDL Configuration Register 4 31 24 Clk_Dly yyh c Half Period of the System Clock 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers ...

Page 251: ...lk_Dly yyh c Half Period of the Sys Clk 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers 7 0 Act_Dly xxh c From SW_Recal or Direct Write 0x0x1x68h DDR PDL Configuration Register 9 31 24 Clk_Dly yyh c Half Period of the Sys Clk 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers 7 0 ...

Page 252: ...h c SW_Cal_Dly in of Buffers 7 0 Act_Dly xxh c FromSW_RecalorDirectWrite 0x0x1x78h DDR PDL Config Register 13 31 24 Clk_Dly yyh c HalfPeriodoftheSystemClock 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers 7 0 Act_Dly xxh c FromSW_RecalorDirectWrite 0x0x1x7Ch DDR PDL Config Register 14 31 24 Clk_Dly yyh c HalfPeriodoftheSystemClock 23 16 ...

Page 253: ... yyh c Half Period of the System Clock 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers 7 0 Act_Dly xxh c From SW_Recal or Direct Write 0x0x1x8h DDR PDL Config Register 17 31 24 Clk_Dly yyh c Half Period of the System Clock 23 16 SW_Cal_Dly xxh B FSB Delay for DQS 100 MHz 69h 133 MHz 6Bh 15 8 Cal_Dly yyh c SW_Cal_Dly in of Buffers 7 0 Act...

Page 254: ...nsistorDrv Strength 17 16 NDrvMDAT 10b B Weakest 00b 11b Strongest MDATNTransistorDrvStrength 15 14 Reserved 00b r 13 11 PSlewDQS 101b B Slowest 000b 111b Fastest DQS Rising Edge Slew Rate 10 8 NSlewDQS 101b B Slowest 000b 111b Fastest DQS Falling Edge Slew Rate 7 4 Reserved 0h r 3 2 PDrvDQS 11b B Weakest 00b 11b Strongest DQS P Transistor Drv Strength 1 0 NDrvDQS 10b B Weakest 00b 11b Strongest D...

Page 255: ... Transistor Drv Strength 17 16 NDrvCLK 10b B Weakest 00b 11b Strongest CLK N Transistor Drv Strength 15 14 Reserved 00b r 13 11 PSlewCS 101b B Slowest 000b 111b Fastest CS Rising Edge Slew Rate 10 8 NSlewCS 101b B Slowest 000b 111b Fastest CS Falling Edge Slew Rate 7 4 Reserved 0h r 3 2 PDrvCS 11b B Weakest 00b 11b Strongest CS P Transistor Drv Strength 1 0 NDrvCS 10b B Weakest 00b 11b Strongest C...

Page 256: ...ansistor Drv Strength 17 16 NDrvCMDB 10b B Weakest 00b 11b Strongest CMDB N TransistorDrv Strength 15 14 Reserved 00b r 13 11 PSlewCMDA 101b B Slowest 000b 111b Fastest CMDA Rising Edge Slew Rate 10 8 NSlewCMDA 101b B Slowest 000b 111b Fastest CMDA Falling Edge Slew Rate 7 4 Reserved 0h r 3 2 PDrvCMDA 11b B Weakest 00b 11b Strongest CMDAP Transistor Drv Strength 1 0 NDrvCMDA 10b B Weakest 00b 11b ...

Page 257: ...nsistor Drv Strength 17 16 NDrvMAB 10b B Weakest 00b 11b Strongest MAB N Transistor Drv Strength 15 14 Reserved 00b r 13 11 PSlewMAA 101b B Slowest 000b 111b Fastest MAA Rising Edge Slew Rate 10 8 NSlewMAA 101b B Slowest 000b 111b Fastest MAA Falling Edge Slew Rate 7 4 Reserved 0h r 3 2 PDrvMAA 11b B Weakest 00b 11b Strongest MAA P Transistor Drv Strength 1 0 NDrvMAA 10b B Weakest 00b 11b Stronges...

Page 258: ...unction 0 Registers Device 1 registers provide the necessary controls for the AMD 761 system controller s internal PCI to PCI bridge and AGP controller functions The PCI to PCI bridge functions as a logical bridge between the Host PCI bus and the AGP interface and contains the normal PCI configuration registers for such a device Most of these bits are read only ...

Page 259: ...RR 0b r 23 FastB2B 0b r 22 UDF 0b r 21 66M 1b r Support 66 MHz on device 1 20 Cap_Lst 0b r 19 10 Reserved 00b 00h r 9 FBACK 0b 8 SERR System Error Enable yb u 0 Disable 1 Enable 7 Step 0b r 6 PERR 0b r 5 VGA Palette Snoop 0b r 4 MWINV 0b r 3 SCYC 0b r 2 MSTR 1b B DMA enabled on APCI 1 MEM 1b B Memory accessenable on APCI 0 IO 1b B IO access Enabled on APCI 0x1x0x08h PCI Rev ID and Class Code 31 24...

Page 260: ..._Type 01h r 15 8 Pri_Lat_Timer 40h B 7 0 Reserved 00h r 0x1x0x18h AGP PCI Sub Bus Num Secondary Latency Timer 31 24 Secon_Lat_Timer 40h B 23 16 Sub_Bus_Num 01h B 15 8 Secon_Bus_Num 01h B 7 0 Pri_Bus_Num 00h r KEY B Mandatory BIOS function A AGP setup by BIOS c Calculated set by AMD 761 internal logic P Power management setup by BIOS o Setup by OS or OS driver F Performance enhancement set by BIOS ...

Page 261: ...to forward I O transactions from one interface to another 11 8 IOLimit_R 1h r Lower 4 bits defining top address that is used by the bridge to forward I O transactions from one interface to another 0x1 indicates that 32 bit I O address decoding is available 7 4 IOBase 15 12 xh B Writable 4 bits that defines bottom address that is used by the bridge to forward I O transactions from one interface to ...

Page 262: ...bits are 0xFFFFF for 1 Mbyte granularity 3 0 Reserved 0h r 0x1x0x24h AGP PCI Prefetchable Memory Limit and Base 31 20 MLim 31 20 xxxh B Prefetchable Memory Limit Address defining top address to be used by AGP target graphics controller for control registers and buffers The lower 20 bits are 0xFFFFF for 1 Mbyte granularity 19 16 0h r 15 4 MBase 31 20 xxxh B Prefetchable Memory Base Address defining...

Page 263: ...ses passed to the AGP PCI bus 0x1x0x3Ch AGP PCI Interrupt and Bridge Control 31 24 Reserved 00h r 23 Bridge_Fast_B2B_En 0b r 22 Secon_Bus_ Reset 0b r 21 Mas_Abort_Mode 0b r 20 Reserved 0b r 19 VGA_En 1b B 18 ISA_En 0b B 17 SERR_En yb u 16 Par_Resp_En 0b r 15 8 Int_Pin xxh B Enabled by 0x1x0x40 0 7 0 Int_Line xxh B 0x1x0x40h Miscellaneous Device 1 Control 31 1 Reserved 000b 0000000h r 0 Int_Pin_Cnt...

Page 264: ...252 Recommended BIOS Settings Chapter 7 AMD 761 System Controller Software BIOS Design Guide 24081D February2002 Preliminary Information ...

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