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AMD-761™ System Controller Programmer’s Interface
Chapter 2
AMD-761™ System Controller Software/BIOS Design Guide
24081D—February 2002
Preliminary Information
PCI Command and Status
Dev0:F0:0x04
Register Description
31
30
29
28
27
26
25
24
Bit
PERR_Rcv
SERR_Sent
Mas_ABRT
Trgt_ABRT
Trgt_ABRT
_ Signaled
DEVSEL_Timing
Data_PERR
Reset
0
0
0
0
0
0
1
0
R/W
R
R/W1C
R/W1C
R/W1C
R
R
R
23
22
21
20
19
18
17
16
Bit
Fast_B2B
UDF
66M
Cap_Lst
Reserved
Reset
0
0
0
1
0
0
0
0
R/W
R
15
14
13
12
11
10
9
8
Bit
Reserved
FBACK
SERR
Reset
0
0
0
0
0
0
0
0
R/W
R
R/W
7
6
5
4
3
2
1
0
Bit
STEP
PERR
VGA
MWINV
SCYC
MSTR
MEM
I/O
Reset
0
0
0
0
0
1
0
0
R/W
R
R/W
R