Pike
Technical
Manual
V5.2.3
88
Camera interfaces
Camera
interfaces
The
cameras
also
have
an
advanced
register
which
allows
even
more
precise
image
capture
delay
after
receiving
a
hardware
trigger.
Trigger delay advanced register
The
advanced
register
allows
the
start
of
the
integration
to
be
delayed
by
max.
2
21
µs,
which
is
max.
2.1
s
after
a
trigger
edge
was
detected.
Register
Name
Field
Bit
Description
0xF0F00834
TRIGGER_DELAY
Presence_Inq
[0]
Presence
of
this
feature:
0:N/A
1:
Available
Abs_Control
[1]
Absolute
value
control
O:
Control
with
value
in
the
value
field
1:
Control
with
value
in
the
absolute
value
CSR.
If
this
bit=1
the
value
in
the
value
field
has
to
be
ignored.
---
[2
to
5]
Reserved
ON_OFF
[6]
Write
ON
or
OFF
this
feature
Read:
Status
of
the
feature
ON=1
OFF=0
---
[7
to
19]
Reserved
Value
[20
to
31] Value
Table 28: Trigger Delay CSR
Register
Name
Field
Bit
Description
0xF1000400
TRIGGER_DELAY
Presence_Inq
[0]
Indicates
presence
of
this
feature
(read
only)
---
[1
to
5]
-
ON_OFF
[6]
Trigger
delay
on/off
---
[7
to
10]
-
DelayTime
[11
to
31] Delay
time
in
µs
Table 29: Trigger delay advanced CSR
