Allen-Bradley POINT I/O 1734-VHSC24, User Manual, Page: 36 / 64

Publication 1734-UM003A-EN-P - August 2000
3-8 Very High Speed Counter Module Input and Output Data
In the counter modes ( counter [0], x1 encoder [1], x2 encoder [2], pwm
[3], x4 encoder [4]
), it attenuates the counter display, for example, 20
divides count+1 by 20. The value may be in the range 0 < value
≤
255.
The result of requesting a number other than 1 performs the function:
(COUNT + 1) / ATTENUATION. This is useful for scaling a large
counter value to a smaller 16 bit value or a percentage. 1 is the default
setting and zero reverts to 1 to prevent a divide by zero.
Active Output Assembly (Configuration Word 4)
This byte permits selection of either assembly 105 (0x69 - Counter/
Output Control) or 106 (0x6A - PWM Value) for poll consumption.
Entering a zero will cause the default assembly, 105, to be selected.
Time Base/Pulse Width Modulation (PWM) Period
(Configuration Word 5)
This word sets the fundamental time base for the counter. Its
resolution is in milliseconds with minimum 10ms intervals (i.e. an
interval of 10 milliseconds is a value of 10, 1 second is 1000). The
maximum value that may be programmed is 3 seconds (3000). The
time base must be entered when the
PWM [3]
and
rate measurement
[7] configurations are used.
Gate Interval (Configuration Word 6)
This byte sets the counter’s gate interval using the time base setting as
its time unit. (i.e. its resolution is determined by the time base). The
actual gate interval is the product of the time base and the gate
interval (ex: 50ms gate interval may be produced with a time base of
10 and a gate interval of 5 or a time base of 50 and a gate interval of
1). The maximum value of the product of time base x gate interval is 3
seconds. The gate interval must be entered when the
PWM [3]
and
rate measurement [7] configurations are used. The maximum value is
200.