Allen-Bradley POINT I/O 1734-VHSC24, User Manual, Page: 35 / 64

Publication 1734-UM003A-EN-P - August 2000
Very High Speed Counter Module Input and Output Data 3-7
Filter Selection (Configuration Word 2)
This byte sets the A/B/Z input filters
Filter Selection
Decimal Position (Configuration Word 3)
This byte changes the significant digits of the frequency or counter
display.
In the frequency modes (
period/rate [5]
,
continuous/rate [6]
,
rate
measurement [7] ) for example, a -2 will move the decimal point left 2
places, dividing the frequency value by 100, a +1 moves it right,
multiplying by 10. The firmware checks for placement to be in the
range -4
≤
value
≤
+2. A value outside the range will move the
decimal point to the zero position and assert the programming error
(PE) bit. Moving the decimal point to the left (i.e. negative), allows
high frequencies, commonly present in rate measurement mode, to fit
within a single 16 bit word. Moving the decimal point to the right (i.e.
positive), allows low frequencies, commonly present in period and
continuous rate modes, to have resolution displayed to 0.1Hz and
0.01Hz. Frequencies should be kept below 3.2kHz for 0.1Hz
resolution and below 320Hz for 0.01Hz. Scalars of Z/128, Z/64, Z/32
and Z/16 should
not be used when positioning is applied. 0 is the
default setting.
07 06 05 04 03 02 01 00
0 ZF BF AF FS
0 0 0 0 No Filter
0 0 0 1 50kHz (10
µ
s + 0
µ
s/-1.6
µ
s)
0 0 1 0 5kHz (100
µ
s + 0
µ
s/-13.2
µ
s)
0 1 0 0 500Hz (1.0ms + 0
µ
s/-125
µ
s)
1 0 0 0 50Hz (10ms + 0ms/-1.25ms)
0 A input not filtered
1 A input filtered
0 B input not filtered
1 B input filtered
0 Z input not filtered
1 Z input filtered