Allen-Bradley POINT I/O 1734-VHSC24, User Manual, Page: 17 / 64

Publication 1734-UM003A-EN-P - August 2000
About the Very High Speed Counter Modules 1-9
New Data Indicator
A two bit counter, C1 & C0, is updated every time an "event" occurs,
indicating that new data is available in the Stored/Accumulated Count
words. Events are defined as:
Any active gate transition in any of the Store Count (Counter or
Encoder) modes;
The end of the gate sample period in either the Period / Rate ,
Continuous / Rate or PWM modes;
The end of the programmed sample period in the Rate
Measurement mode.
To use these bits reliably, acquisition of data from the Counter Module
must occur faster than the events, which cause C1/C0 to increment.
When C1/C0 is updated, a Change Of State (COS) message can be
sent.
Default Configuration
The module’s default configuration on startup will be:
•
Counter Mode
•
50Hz filter on A, B and Z
•
No time base
•
Active Output Assembly = 105
•
Rollover = 0x00FFFFFF
•
Preset = 0
•
No scalar
•
Output 0 untied
•
Output 1 untied
•
Window comparators = 0
•
Counter Control Safe State = 0
•
Output Control Safe State = 0
To modify the default settings to those required for your application,
refer to chapter 3.