4 Connecting Mainframes to the Controller PC
Interconnecting Slave Mainframes
4-12
Agilent 81250 ParBERT Installation Guide, May 2004
The following figure illustrates the complete wiring of a system with two
expander frames.
IEEE 1394 link
Master mainframe
(Clockgroup 1)
1st slave mainframe
(Clockgroup 2)
2nd slave mainframe
(Clockgroup 3)
Figure 19 Connections of a Three-Mainframe System
If you do not interconnect the clock modules with clock reference cables,
then you set up an Agilent 81250 Parallel Bit Error Ratio Tester that
comprises three independent ParBERT systems.
Independent ParBERT systems can be frequency-synchronized by
connecting the TRIGGER OUT port of one system to the CLOCK/REF
INPUT or CLOCK INPUT port of the second system. This requires that the
parameters of the clock modules are set accordingly with the ParBERT
user software.
Frequency-synchronization does not mean phase-synchronization.
TIP
Summary of Contents for 81250
Page 1: ...Agilent Parallel Bit Error Ratio Tester 81250 ParBERT Installation Guide Agilent Technologies ...
Page 12: ...1 About this Manual Document History 1 6 Agilent 81250 ParBERT Installation Guide May 2004 ...
Page 30: ...2 Introduction Unpacking ParBERT 2 18 Agilent 81250 ParBERT Installation Guide May 2004 ...
Page 139: ...Declaration of Conformity Appendix Agilent 81250 ParBERT Installation Guide May 2004 10 3 ...
Page 141: ...Site Attenuation Requirements Appendix Agilent 81250 ParBERT Installation Guide May 2004 10 5 ...
Page 142: ...Appendix Site Attenuation Requirements 10 6 Agilent 81250 ParBERT Installation Guide May 2004 ...
Page 145: ......