Advantech MIC-5332, User Manual

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Figure 5.16 Chipset Configuration
5.5.1 North Bridge
Users can set up all parameters related to the IOH function in the North Bridge page.
Moreover, the MIC-5332 BIOS allows users to configure the PCIe link speed (gen1,
gen2 or gen3) and its functions visible (x16, x8x8, x8x4x4, x4x4x8 or x4x4x4x4) in the
IOH configuration submenu. Also, the Sandy Bridge CPU supports two QPI channels.
Users can configure the related settings in the QPI configuration submenu.
Table 5.10 North Bridge Configuration
Feature Default Description
IOH Configuration Submenu IOH Configuration Page
QPI Configuration Submenu QPI Configuration Page
Compatibility RID Enabled
Support for Compatibility Revision ID (CRID)
Functionality mentioned in Sandy Bridge Bios spec
Total Memory Display only Show total memory capacity
Current Memory
Mode
Display only Show current memory mode
Current Memory
Speed
Display only Show current memory speed
Mirroring Display only Show mirroring status
Sparing Display only Show Sparing status
Memory Mode Independent Select the mode for memory initialization.
NUMA Enabled Enable or Disable Non uniform Memory Access.
DDR Speed Auto Force DDR Speed
Channel Interleaving Auto Select different Channel Interleaving setting.
Rank Interleaving Auto Select different Rank Interleaving setting.
Patrol Scrub Enabled Enable/Disable Patrol Scrub
Demand Scrub Disabled Enable/Disable Demand Scrubbing Feature
Data Scrambling Disabled Enable/Disable Data Scrambling.
Device Tagging Disabled Enable/Disable Device Tagging.
DIMM Information Display Only Show current DIMMs status in use.