MIC-5332 are listed as table 2.7.
Figure 2.2 DIMM slots on the MIC-5332
DIMM Type
RDIMMs
UDIMMs
LRDIMMs
Size
2GB, 4GB, 8GB, 16GB and
32GB
2GB, 4GB and 8GB
8GB, 16GB and 32GB
Speed
1066 / 1333 / 1600
1066 / 1333
Ranks
SR, DR, QR (only for
1066/1333)
SR, DR
QR
Table 2.7: Supported DIMM Configurations
2.
Note
:
2G, 4G and 8GB DDR3 DRAM technologies are supported for these devices:
UDIMMs x8, x16
RDIMMs x4, x8
LRDIMMs x4, x8
Up to 4 ranks supported per memory channel: 1, 2 or 4 ranks per DIMM.
Supports a maximum of 256GB DDR3-1600 memory.
2.3.2 RAS Mode
Four DRAM RAS modes are supported by the memory controller which can be
configured in BIOS setup menu.
Independent Channel Mode (Default)
Channels can be populated in any order in Independent Channel Mode. All four
channels may be populated in any order and have no matching requirements. All
channels must run at the same interface frequency, but individual channels may
run at different DIMM timings (RAS latency, CAS latency, etc.).
Rank Sparing Mode
In Rank Sparing Mode, one rank is a spare of the other ranks on the same
channel. The spare rank is held in reserve and is not available as system
memory. The spare rank must have identical or larger memory capacity than all
the other ranks (sparing source ranks) on the same channel. After sparing, the
sparing source rank will be lost.
Summary of Contents for MIC-5332
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Page 10: ...Chapter 1 Product Overview This chapter briefly describes the MIC 5332 ...
Page 15: ...Chapter 2 Board Features This chapter describes the MIC 5332 hardware features ...
Page 43: ...Figure 3 10 Jumper Locations JP1 JP5 JP6 ...
Page 44: ...Chapter 4 Hardware Management This chapter describes the IPMC firmware features ...
Page 105: ... root localhost ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x01 section ...
Page 108: ...Appendix A IPMI PICMG Command Subset Supported by IPMC ...
Page 120: ...33 48V_A 48V input feed A 34 48V_B 48V input feed B ...