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Zone 2 J23 pin out – Base Interface and Fabric Interface

J23

Pin

Row

A

B

C

D

E

F

G

H

1

FI_CH2

Tx2+

FI_CH2

Tx2

‐

FI_CH2

Rx2+

FI_CH2

Rx2

‐

FI_CH2

Tx3+

FI_CH2

Tx3

‐

FI_CH2

Rx3+

FI_CH2

Rx3

‐

2

FI_CH2

Tx0+

FI_CH2

Tx0

‐

FI_CH2

Rx0+

FI_CH2

Rx0

‐

FI_CH2

Tx1+

FI_CH2

Tx1

‐

FI_CH2

Rx1+

FI_CH2

Rx1

‐

3

FI_CH1

Tx2+

FI_CH1

Tx2

‐

FI_CH1

Rx2+

FI_CH1

Rx2

‐

FI_CH1

Tx3+

FI_CH1

Tx3

‐

FI_CH1

Rx3+

FI_CH1

Rx3

‐

4

FI_CH1

Tx0+

FI_CH1

Tx0

‐

FI_CH1

Rx0+

FI_CH1

Rx0

‐

FI_CH1

Tx1+

FI_CH1

Tx1

‐

FI_CH1

Rx1+

FI_CH1

Rx1

‐

5

BI_CH1

DA+

BI_CH1

DA

‐

BI_CH1

DB+

BI_CH1

DB

‐

BI_CH1

DC+

BI_CH1

DC

‐

BI_CH1

DD+

BI_CH1

DD

‐

6

BI_CH2

DA+

BI_CH2

DA

‐

BI_CH2

DB+

BI_CH2

DB

‐

BI_CH2

DC+

BI_CH2

DC

‐

BI_CH2

DD+

BI_CH2

DD

‐

7

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

8

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

9

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

10

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

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Summary of Contents for MIC-5332

Page 1: ...User Manual MIC 5332 AdvancedTCA 10GbE Dual Socket CPU Blade with Intel Xeon E5 2600 series EP Processors ...

Page 2: ...ision History Revision Index Brief Description of Changes Date of Issue 0 1 Initial Draft November 15th 2011 0 2 Modification April 11th 2012 0 3 Modification June 15th 2012 0 4 Modification July 16th 2012 ...

Page 3: ...ident or improper installation Advantech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most of our customers never need to use our repair service If an Advantech product is defective it will be repaired or replaced at no charge during the warranty period For out of warranty repairs yo...

Page 4: ...he instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his or her own expense Technical Support and Assistance 1 Visit the Advantech web site at www advantech com support where you can find the latest information abou...

Page 5: ... type recommended by the manufacturer Discard used batteries according to the manufacturer s instructions Note Notes provide optional additional information Document Feedback To assist us in making improvements to this manual we would welcome comments and constructive criticism Please send all such in writing to support advantech com Packing List RJ45 to DB9 Console Cable x1 p n 1700002270 Mini US...

Page 6: ...he operator s position according to IEC 704 1 1982 is no more than 70 dB A DISCLAIMER This set of instructions is given according to IEC 704 1 Advantech disclaims all responsibility for the accuracy of any statements contained herein Safety Precaution Static Electricity Follow these simple precautions to protect yourself from harm and the products from damage 1 To avoid electrical shock always dis...

Page 7: ...This page is left blank intentionally ...

Page 8: ...form Management IOH I O Controller Hub IPMC Intelligent Platform Management Controller IPMI Intelligent Platform Management Interface MCH Memory Controller Hub NVRAM Non volatile Random Access Memory OOS Out Of Service PCH Platform Controllers Hub PCIe PCI Express PECI Platform Environment Control Interface PICMG PCI Industrial Computer Manufacturers Group PXE Pre boot Execution Environment QPI Qu...

Page 9: ...r Controller SOL Serial Over LAN TCLK Telecom Clock TPM Trusted Platform Module TX Transmit UDIMM Unbuffered DIMMs UHCI Universal Host Controller Interface VLP Very Low Profile XAUI X means ten Attachment Unit Interface ...

Page 10: ...Chapter 1 Product Overview This chapter briefly describes the MIC 5332 ...

Page 11: ...for dual dual star fabric implementations can be added by installing the FMM 5001B Fabric Mezzanine Module FMM Beyond that the FMM type II socket with PCIe x16 connectivity provides extension possibilities for additional front port I O offload and acceleration controllers such as Intel QuickAssist accelerators IPSec offload engines or customer specific logic FMMs not only have higher PCI Express b...

Page 12: ...M 5104 for High Availability HA needs rear I O and dual SAS storage with RAID as well as an optional FMM Please contact Advantech for more information on available RTMs An on board FPGA design facilitates customer specific modifications and the core board design can be modified or adapted to other form factors through Advantech s DMS customization services Figure 1 1 MIC 5332 Overview Top Side ...

Page 13: ... 2 Block Diagram The hardware implementation is shown in the following block diagram Refer to Table 1 1 next page for the detailed product technical specification Option Figure 1 2 MIC 5332 Block Diagram ...

Page 14: ... Configurations Note Support max 256GB using 8 pieces of 32GB DDR3 1600 VLP DIMM modules 1 4 Related Products Model Name Configurations RTM 5104 I O extension ATCA RTM for MIC 5332 FMM 5001BE Dual 10GE Module with 2x fabric ports for dual dual star support based on i82599EB FMM 5001FE Dual 10GE Module with 2x SFP front IO based on i82599ES FMM 5002E Server Graphics Module with external VGA Port FM...

Page 15: ...Chapter 2 Board Features This chapter describes the MIC 5332 hardware features ...

Page 16: ... x 10 100 1000BASE T or SFP through i350 MAC PHY 1x 10 100 1000 BASE T Chipset LAN USB 2 0 2 x Type A ports Operating System Compatibility WindRiver PNE LE 4 2 RedHat Enterprise 5 7 6 2 CentOS 6 1 Windows Server 2008 IPMC BMC Controller NXP LPC1768 Cortex M IPMI Compliant with IPMI 1 5 using Advantech IPMI code base Watchdog Timer Supervision 1 for x86 BIOS POST OS Boot Application Interval IPMI c...

Page 17: ...lt in memory controller It is a two chip platform CPU and PCH as opposed to traditional three chip platforms CPU MCH and IOH The Intel Xeon E5 2600 series feature per socket two Intel QuickPath Interconnect point to point links capable of up to 8 0 GT s up to 40 lanes of Gen 3 PCI Express links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express Gen 2 interface with a peak transfer rate of 5 0 GT ...

Page 18: ...current traffic and true isochronous transfer capabilities Base functionality is completely software transparent permitting current and legacy software to operate normally New for C604 chipset the DMI interface operates at 5 0 GT s 2 2 4 PCI Express Port Configuration Intel Xeon E5 2600 series processors support 40 PCI Express Gen3 ports They are configured to two x16 ports one x8 port and five x4...

Page 19: ...des of operation to support different operating system conditions In the case of a Native IDE enabled operating system the C600 PCH utilizes two controllers to enable all six ports of the bus The first controller Device 31 Function 2 supports ports 0 3 and the second controller Device 31 Function 5 supports ports 4 and 5 When using a legacy operating system only one controller Device 31 Function 2...

Page 20: ... USB 2 0 high speed support The USB port connection in the MIC 5332 is listed in table 2 6 Port No Description 0 1 Front Panel Ports 2 3 USB devices on a FMM 4 7 Not used 8 11 USB devices on an RTM connect to Zone 3 12 13 Not used Table 2 6 USB Ports C on the MIC 5332 2 2 8 Real time Clock RTC Because there is no battery assembled on the MIC 5332 the integrated real time clock is fed by IPMC manag...

Page 21: ...e supported by the memory controller which can be configured in BIOS setup menu Independent Channel Mode Default Channels can be populated in any order in Independent Channel Mode All four channels may be populated in any order and have no matching requirements All channels must run at the same interface frequency but individual channels may run at different DIMM timings RAS latency CAS latency et...

Page 22: ...dentically with regards to size and organization DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel 1 and across Channel 2 and Channel 3 must be populated identically 3 Note The memory channel mode can be configured in BIOS setup menu described in Chapter 5 AMI BIOS Setup Regarding the correct installation of memory modul...

Page 23: ...ch as I O acceleration security enhancement and virtualization Flow director boosts 10GbE performance efficiency on multi core CPUs and VMDq2 increases the number of virtual machine up to 64 For additional technical details of Intel JL82599EB please visit www intel com Additional fabric channels 3 and 4 can be supported via the FMM see Appendix DE Redrivers for e keying support and for improved ba...

Page 24: ...ppable Customer may ask for a customized RTM please contact your Advantech representative or choose the Advantech RTM 5104 For detailed specifications please refer to table 2 9 For the detailed pin list of the Zone 3 interface please see Appendix D Zone 3 Interface RTM Pin Assignment Model Name Storage USB LAN COM FMM Support External SAS Connectors RTM 5104SE 2x SAS 1 2x RJ45 1x miniUSB 9 RTM 510...

Page 25: ... please contact your Advantech representative or choose from the following Advantech FMM 5000 options For detailed specifications please refer to table 2 10 Model Name Description Chip I O FMM 5001B Additional 10GbE Support for Dual Dual Star FI Intel 82599 N A FMM 5001F Additional 10GbE Support for Dual Dual Star FI Intel 82599 2x SFP FMM 5002 Server Graphic Support for Debug Bring Up SM750 1x VG...

Page 26: ...Chapter 3 Installation This chapter describes the procedure to install the MIC 5332 into a chassis Peripherals DIMMs SSD installation jumper setting and LED definition are also described here ...

Page 27: ...ents when installing memory modules Mixing of Registered and Unbuffered DIMMs is not allowed To optimize the memory performance by balanced sharing the load on each channel of a socket Advantech requires to use the identical memory modules with the same density rank speed timing parameters and other factors Although unbalanced configurations might work they are not supported by Advantech For suppo...

Page 28: ...ctors of the empty DIMM socket 4 Repeat steps 2 3 for the remaining modules to be removed 3 3 Console Terminal Setup The MIC 5332 contains five serial interfaces listed as below More details about setup will described through an example to show how to setup the console for the MIC 5332 with the following example sections COM1 RJ45 on the front panel COM2 miniUSB on the front panel Serial over LAN ...

Page 29: ... will then switch the output to this interface as this is the latest request The previous RJ45 link will consequently become disconnected UART MUX Zone3 UART1 UART2 SoL miniUSB RJ45 Step1 User establishes the console link through any available output e g RJ 45 ...

Page 30: ...UX Zone3 UART1 UART2 SoL miniUSB RJ45 Step2 When the user plugs another console cable into the MIC 5332 e g miniUSB the UART MUX will switch the output from RJ45 to this new interface last in first serve rule ...

Page 31: ...e function on the MIC 5322 with a RJ45 to DB9 cable no additional driver is needed Prerequisite RJ45 to DB9 cable mini USB COM2 The MIC 5332 uses a USB to UART bridge called CP2102 GM from Silicon Labs to UART MUX Zone3 UART1 UART2 SoL miniUSB RJ45 X Step3 The original link RJ 45 becomes disconnected ...

Page 32: ... www silabs com products interface usbtouart Pages default aspx Serial over LAN SoL User may also establish the console via SoL function which is described in section 4 6 Serial over LAN SoL Prerequisite RJ45 Ethernet cable and IPMItool see section 4 6 2 1 IPMItool Note When SoL is used as the console terminal please skip Section 3 3 2 and 3 3 3 UART1 UART2 Zone3 The MIC 5332 connects two UART int...

Page 33: ...tem and then Hardware Let us assume the CP210x USB to UART Bridge Controller has been assigned with COM12 you can open up PuTTY and begin the configuration as shown below If you use the RJ45 COM1 and a serial port on the terminal PC please use the COM port number of that serial port instead of COM12 Specify COM12 under serial line and 115200 for speed no parity no flow control Check Serial for con...

Page 34: ... Configurations If the connection is successful and the user enters BIOS setup menu upon boot the MIC 5332 BIOS setup menu will be displayed on the PuTTY screen Figure 3 4 MIC 5332 BIOS setup menu shown on PuTTY screen ...

Page 35: ...receptacle 4 Hold both handle ejectors on either side of the board and then close them to make the board becomes fully seated Make ensure the handles are latched securely 5 Fasten the retaining thumbscrews 6 The blue hot swap LED on the front panel will show a ONÆBlinkÆOFF transition to indicate a normal power on sequence of the MIC 5332 Once the FW and payload has been successfully activated the ...

Page 36: ...ubsystem on the blade has been powered down the blue hot swap LED will light up which indicates the board is ready to be removed 4 Unfasten the retaining thumbscrews 5 Unlock the other handle and fully open both handles push handles outwards to extract the board 6 Pull the MIC 5332 out of the chassis Figure 3 6 Unlock the ejector handle Caution DO NOT attempt to extract the board when blue LED is ...

Page 37: ... blade refer to figure 3 9 and make sure the module and the carrier connectors are aligned Insert the FMM module until the connector is firmly seated in the socket 2 Install the screws refer to figure 3 10 and power on the MIC 5332 to make sure the installation is completed 3 To remove the FMM follow the procedure in reverse Figure 3 7 FMM Module top left and bottom right views Installation w scre...

Page 38: ...Figure 3 8 MIC 5332 w FMM module and SSD Bracket locations Figure 3 9 Locate the FMM site on the blade SSD Bracket FMM Module ...

Page 39: ...alled with a specific daughter board and bracket from the factory For more details please contact your Advantech representative to obtain a list of compliant SSDs and CFast cards 3 4 5 Front Panel The MIC 5332 is 100 compatible to AdvancedTCA specifications All LED signals are shown on the front panel Users can refer to section 3 6 LED definition to know the details of the board operating status P...

Page 40: ... starting please refer to table 3 2 to learn the LED signal identification in this manual In the following section we take amber as an example Handle Top side Retaining Thumbscrews Retaining Thumbscrews Handle Bottom side FI Channel 1 2 Status LEDs BI Channel1 2 Status LEDs SAS Status LEDs Dual Color User LEDs USB2 USB1 COM2 miniUSB Hot Swap LED Button1 Reserved Button2 Reserved OOS LED Health LED...

Page 41: ... Active No Link SAS Status 1 2 3 4 Active Failure Active Failure USR Status 1 2 3 4 N A User defined User defined LAN Port 1 2 3 Speed 1Gb s 100Mb s 10Mb s Link Active Link Active No Link Out of Service System out of service System normal Health Status FW active payload enabled FW active payload disabled FW is not active Hot swap Board is not activated ready to be swapped Board is de activating un...

Page 42: ... section describes the jumpers on the MIC 5332 for reference In normal operation users are not to access or modify jumpers Jumper Feature Setting Operation JP1 Clean CMOS 1 2 Closed Normal Mode Default 2 3 Closed Clean CMOS JP6 GND Connection 2 3 Closed Shelf GND open to logic GND Default 1 2 Closed Shelf GND short to logic GND Table 3 4 Jumper Settings ...

Page 43: ...Figure 3 10 Jumper Locations JP1 JP5 JP6 ...

Page 44: ...Chapter 4 Hardware Management This chapter describes the IPMC firmware features ...

Page 45: ... Its core is a NXP LPC1768 Cortex M based CPU running on an RTOS For the list of supported IPMI commands by Advantech please refer to Appendix A IPMI PICMG Command Subset Supported by IPMC A Lattice LFXP2F17 FPGA is used to provide additional connectivity for the IPMC and payload It provides extension interfaces with configurable routing options as well as some additional stand alone functionality...

Page 46: ...PMB address to the slot location within the chassis 4 2 1 2 IPMB L Interface IPMB L is the interface between the IPMC and a Module Management Controller MMC on a compliant RTM such as the RTM 5104 It is connected to the IPMB L bus through I2 C bus isolators 4 2 1 3 System Interface The x86 subsystem referred to as payload may communicate with the IPMC via a KCS interface The KCS commands will be t...

Page 47: ...ead out the actual selected IPMI over LAN Serial over LAN interface and to change the selection LAN controller interface selection settings 00h Front panel LAN IO 01h LAN BI default Read LAN Interface selection Response Change LAN Interface selection Response LAN controller channel selection and priority In addition to the selected LAN controller interface users may need to configure each single L...

Page 48: ...ue is 0 Read LAN channel selection priority Response Change LAN channel selection priority Response 4 2 2 System Event Log SEL The IPMC supports a non volatile System Event Log SEL which stores events of onboard sensors as well as hosted FRUs such as the RTM modules The SEL contains 8192 bytes 512 sel entries and new events will overwrite the old ones after the SEL is full Besides putting logs in ...

Page 49: ...gth 0xCC FRU file ID frudata xml Additional custom Mfg Info fields unused C1h No more info fields 0xC1 00h unused space 0x00 0x00 0x00 0x00 Board area checksum calculated Table 4 1 Board Information Area Field description Board information Format version 0x01 Product area length calculated Language code 0x19 English Product Manufacturer type length 0xC9 Product manufacturer Advantech Product name ...

Page 50: ...esholds are classified as Non critical Critical or Non recoverable When different thresholds are reached different actions will be given by the shelf manager accordingly for details please refer to table 4 3 Threshold Description UNR Upper Non recoverable UC Upper Critical UNC Upper Non critical LNC Lower Non critical LC Lower Critical LNR Lower Non recoverable Table 4 3 Sensor Threshold Descripti...

Page 51: ...ld sensor DC DC input voltage V48_B VOL Threshold sensor DC DC input voltage BAT_3_0 VOL Threshold sensor Battery Voltage SB_3_3 VOL Threshold sensor AUX voltage 3 3V SB_5_0_VOL Threshold sensor AUX voltage 5V PAY_3_3 VOL Threshold sensor payload voltage 3 3V PAY_5_0 VOL Threshold sensor payload voltage 5V PAY_12 VOL Threshold sensor payload voltage 12V LAN_1_0 VOL LAN chip voltage i350 LAN_1_2 VO...

Page 52: ...ure PECI CPU0_DIMM1 TMP Threshold sensor DIMM temperature PECI CPU0_DIMM2 TMP Threshold sensor DIMM temperature PECI CPU0_DIMM3 TMP Threshold sensor DIMM temperature PECI CPU1_DIMM0 TMP Threshold sensor DIMM temperature PECI CPU1_DIMM1 TMP Threshold sensor DIMM temperature PECI CPU1_DIMM2 TMP Threshold sensor DIMM temperature PECI CPU1_DIMM3 TMP Threshold sensor DIMM temperature PECI LAN_IO BI TMP...

Page 53: ... 1 0 9 1 00 1 05 1 15 1 19 1 21 PCH_1_5 VOL 1 5 1 27 1 34 1 42 1 56 1 64 1 99 CPU0_0_85 VOL 0 85 0 75 0 79 0 85 0 95 1 00 1 40 CPU0_1_05 VOL 1 05 0 75 0 95 1 00 1 10 1 15 1 40 CPU0_CORE VOL 1 10 0 55 1 40 CPU0_1_80 VOL 1 80 1 55 1 62 1 75 1 89 1 95 2 00 CPU1_0_85 VOL 0 85 0 75 0 79 0 85 0 95 1 00 1 40 CPU1_1_05 VOL 1 05 0 75 0 95 1 00 1 10 1 15 1 40 CPU1_CORE VOL 1 10 0 55 1 40 CPU1_1_80 VOL 1 80 ...

Page 54: ...orts TI TMP75 and NI LM86 as temperature sensors When the temperature is crossing a threshold the event will not only be logged but the shelf manager will also adjust the system fan speed accordingly Advantech firmware polls all temperature sensors once per second Sensor Name Value LNR LCR LNC UNC UCR UNR V48 TMP 30 5 0 5 80 90 100 INTAKE0 TMP 30 5 0 5 65 75 85 OUTLET1 TMP 30 5 0 5 65 75 85 PCH TM...

Page 55: ...tchdog sensor is supported according to the Watchdog 2 sensor type listed in the IPMI specification 4 3 3 6 FW Progress Sensor The IPMC SDR contains a FW Progress sensor in order to support logging of the OS boot process The IPMC supports adding and forwarding of SEL entries from the BIOS OS system firmware progress events by sending Add sel entry commands with the matching sensor type to the IPMC...

Page 56: ...Byte 1 is the IPMI header which is a fixed value A0 Byte 2 satisfies the component while byte 3 stands for its action Table 4 8 shows the supported event code structure generated by the integrity sensors on the MIC 5332 Component Action Result Byte 1 Byte 2 IPMC FW Update Successful 0x01 0x00 Update Timeout 0x01 0x04 Update Aborted 0x01 0x02 Activation Failed 0x01 0x21 Manual Rollback Initiated 0x...

Page 57: ... been successfully synced with the ShMM 4 4 Watchdog Timers Two kinds of watchdog timers are built into the IPMC One is used to supervise the IPMC firmware IPMC watchdog and the other is used to supervise the x86 payload BMC watchdog When the IPMC is firmware is stuck the IPMC watchdog bites and resets the IPMC The payload is not affected from this watchdog event The BMC Watchdog of the MIC 5332 I...

Page 58: ... the needs that had traditionally been satisfied by various mechanical connector keying solutions Prevent damage to boards Prevent mis operation Verify fabric compatibility 4 5 1 Zone3 RTM The IPMC on the MIC 5332 and the MMC on the RTM handle the E keying control For the RTM the PCI Express ports need E keying to carry out the hot swap function Brief E keying information of the zone 3 is listed i...

Page 59: ...ntroller through the NC SI interface and sets it in a pass through mode meaning that it can send and receive Ethernet frames through the LAN controller In this mode the GbE controller will use a dedicated MAC address to send and receive packets intended for the IPMC 4 6 2 SoL Preparation 4 6 2 1 IPMItool IPMItool is a utility developed to support the IPMI specification It provides a simple command...

Page 60: ...MItool is ready for use now Before establishing the SoL session the user needs to set related parameters such as user name password and a static IP address of LAN interface via IPMItool The general IPMI command syntax is The example below shows access to the IPMC through LAN RMCP often referred as IPMI over LAN Using KCS or IPMB is similar Note If you have any problem for setup contact Advantech t...

Page 61: ...rial redirected BIOS menu 1 Preconditions for SOL Set IP Address of the Static LAN Interface Command Line Syntax ipmitool I lan H ip A authtype lan set channel command ip address I lan Specifies that Ethernet is used as interface for communications with the IPMC H ip Default IP address of LAN interface 192 168 1 1 A authtype Authentication type depending on supported types by the Shelf Manager NON...

Page 62: ...actual LAN and UART configuration settings chapter x x x Configuration Setting OEM commands before working with SOL 1 Select the LAN interface to be used IO or Base interface 2 Make sure the LAN channel priority is appropriate 3 Select OS UART interface to be used tty0 or tty1 1 3 Default Parameter Following default parameters are good to know for the initial MIC 5332 LAN setup IP Address 192 168 ...

Page 63: ... IPMC IP address root localhost ipmitool lan set 5 ipaddr 172 21 35 104 Setting LAN IP Address to 172 21 35 104 root localhost ipmitool lan print Set in Progress Set Complete Auth Type Support NONE MD5 PASSWORD Auth Type Enable Callback NONE MD5 PASSWORD User NONE MD5 PASSWORD Operator NONE MD5 PASSWORD Admin NONE MD5 PASSWORD OEM IP Address Source Static Address IP Address 192 168 1 1 Subnet Mask...

Page 64: ...must be used to be able to change SOL parameters and establish SOL sessions Following general IPMItool parameters are needed for RMCP and IPMItool sol commands ipmitool I lanplus H IP Address U User P Password sol SOL Command root localhost ipmitool user set password 2 newpassword root localhost ipmitool user set name 2 newuser root localhost ipmitool user list ID Name Callin Link Auth IPMI Msg Ch...

Page 65: ...nfiguration parameters for a given channel sol set parameter value channel This command allows modifying special SOL configuration parameters ipmitool I lanplus IP Address U User P Password sol info Set in progress set complete Enabled false Force Encryption true Force Authentication true Privilege Level ADMINISTRATOR Character Accumulate Level ms 250 Character Send Threshold 32 Retry Count 2 Retr...

Page 66: ...tored in the FRU EEPROM Instead of ipmitool I lanplus IP Address U User P Password sol activate SOL Session operational Use for help terminated ipmitool ipmitool I lanplus IP Address U User P Password sol set SOL set parameters and values set in progress set complete set in progress commit write enabled true false force encryption true false force authentication true false privilege level user ope...

Page 67: ...ue which is representing the real power requirements of the current blade configuration Note The user may disable this function via Advantech s IPMI OEM command ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x06 0x00 0x00 4 8 MAC Address Mirroring All MAC addresses consumed by the MIC 5332 will also be stored in the FRU EEPROM making them available to be read even if the payload is not powered User can ea...

Page 68: ...Request Data b8 00 Command IANA ID MAC address no Response Data Completion Code IANA ID 6 bytes MAC address Net function 0x2E 0x2F OEM Command 0xe2 IANA ID Advantech IANA ID 0x39 28 00 MAC address no 0x00 for Fabric Interface Channel 0 0x01 for Fabric Interface Channel 1 0x02 for Base Interface Channel 0 0x03 for Base Interface Channel 1 0x04 for Front Panel IO Channel 0 0x05 for Front Panel IO Ch...

Page 69: ... with the help of the Get SEL Time IPMI command The IPMC will do a specified number of tries to read out the Shelf Manager time If not successful it will generate an integrity sensor event IPMC synchronization with payload needs to be initiated by the payload itself payload has to use and issue the Get Set SEL Time IPMI commands This is done by BIOS and can be performed by an OS driver via the KCS...

Page 70: ...Chapter 5 AMI APTIO BIOS Setup This chapter describes how to configure the AMI APTIO BIOS UEFI BIOS ...

Page 71: ... can modify BIOS settings and control the special features of the MIC 5332 The setup program uses a number of menus for making changes and turning special features on or off This chapter describes the basic navigation of the MIC 5332 setup screens Figure 5 1 Setup Program Initial Snapshot The BIOS has a built in Setup program that allows users to modify the basic system configuration There is no b...

Page 72: ...reen is shown below The main BIOS setup menu screen has two main frames The left frame displays all the options that can be configured The right frame displays the key legend Above the key legend is an area reserved for a text message Feature Default Description BIOS Vendor Display only American Megatrends Core Version Display only Current BIOS core version in use Compliancy Display only Current U...

Page 73: ...her setup and maintenance 5 3 2 System Time System Date Use this option to change the system time and date Highlight System Time or System Date using the Arrow keys Enter new values through the keyboard Press the Tab key or the Arrow keys to move between fields The date must be entered in MM DD YY format The time is entered in HH MM SS format 5 4 Advanced BIOS Features Setup Select the Advanced ta...

Page 74: ...EA Configuration settings CPU Configuration Submenu CPU Configuration Parameters Runtime Error Logging Submenu Runtime Error Logging Support Setup Options SATA Configuration Submenu SATA Devices Configuration SAS Configuration Submenu SAS Devices Configuration USB Configuration Submenu USB Configuration Parameters UART MUX Configuration Submenu Configure UART output direction Serial Port Console R...

Page 75: ...iority EFI Compatible ROM In case of multiple Option ROMs Legacy and EFI Compatible specifies what PCI Option ROM to launch Above 4G Decoding Disabled Enables or Disables 64bit capable Devices to be Decoded in Above 4G Address Space Only if System Supports 64 bit PCI Decoding PCI Latency Timer 32 PCI Bus Clocks Value to be programmed into PCI Latency Timer Register PERR Generation Disabled Enables...

Page 76: ... BIOS ACPI Auto Configuration Enable Hibernation Enabled Enables or Disables System ability to Hibernate OS S4 Sleep State This option may be not effective with some OS ACPI Sleep State S3 Suspend to RAM Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed Lock Legacy Resources Disabled Enables or Disables Lock of Legacy Resources ...

Page 77: ...s BIOS support for security device O S will not show Security Device TCG EFI protocol and INT1A interface will not be available TPM State Disabled Enable Disable Security Device NOTE Your Computer will reboot during restart in order to change State of the Device Pending Operation Display Only Show current pending operation item TPM Enabled Status Display Only Show current enabled status TPM Active...

Page 78: ... Figure 5 8 CPU Configuration Feature Default Description Socket 0 CPU Information Display Only Socket specific CPU Information Socket 1 CPU Information Display Only Socket specific CPU Information CPU Speed Display Only Show the current CPU speed in use ...

Page 79: ...Number of cores to enable in each processor package Limit CPUID Maximum Disabled Disabled for Windows XP Execute Disable Bit Enabled XD can prevent certain classes of malicious buffer overflow attacks when combined with a supporting OS Windows Server 2003 SP1 Windows XP SP2 SuSE Liniux 9 2 RedHat Enterprise 3 Update 3 Hardware Prefetcher Enabled Enable the Mid Level Cache L2 streamer prefetcher Ad...

Page 80: ... can enable or disable the runtime error logging support via a sub option of the advanced setting default is disabled Figure 5 9 Runtime Error Logging 5 4 7 SATA Configuration Figure 5 10 SATA Configuration ...

Page 81: ... 5332 supports total 4 SAS devices details please refer to section 2 2 6 Users can check each status via this sub option Figure 5 11 SAS Configuration 5 4 9 USB Configuration Feature Default Description SATA Port0 Display only Show current SATA devices in use on the MIC 5332 SATA Port1 Display only SATA Port2 Display only SATA Port3 Display only SATA Port4 Display only SATA Port5 Display only SATA...

Page 82: ...nnected Disable option will keep USB devices available only for EFI application EHCI Hand off Disabled This is a workaround for OSes without EHCI hand off support The EHCI ownership change should be claimed by EHCI deiver USB transfer time out 20 sec The time out value for Control Bulk and Interrupt transfers Device reset time out 20 sec USB mass storage device Start Unit command time out Device p...

Page 83: ...OM1 through the RJ45 connector and another is COM2 through the miniUSB connector Users can configure the related parameters of these two serial port consoles in this submenu For example users can define the terminal type bits per second data bits parity stop bits and others for each serial port console Feature Default Description Console Redirection Enabled Console Redirection Enable or Disable Co...

Page 84: ...k Users can enable or disable the network stack PXe and UEFI via this submenu default is disable Link Console Redirection Settings Submenu The settings specify how the host computer and the remote computer which the user is using will exchange data Both computers should have the same or compatible settings ...

Page 85: ...give a worldwide unique name for the iSCSI initiator Figure 5 16 iSCSI Initiator 5 4 14 Main Configuration Page The MIC 5332 supports five MACs four from the Intel i350 one from the PCH Users can configure legacy boot protocol link speed and Wake On LAN for each of them ...

Page 86: ...AN here Figure 5 17 Main Configuration Page 5 5 Chipset Setup Select the chipset tab from the MIC 5332 setup screen to enter the Chipset Setup screen Users can configure the parameters of north bridge CPU south bridge PCH and ME system display only respectively ...

Page 87: ... Functionality mentioned in Sandy Bridge Bios spec Total Memory Display only Show total memory capacity Current Memory Mode Display only Show current memory mode Current Memory Speed Display only Show current memory speed Mirroring Display only Show mirroring status Sparing Display only Show Sparing status Memory Mode Independent Select the mode for memory initialization NUMA Enabled Enable or Dis...

Page 88: ...led Support for PCH Compatibility Revision ID CRID Functionality SMBus Controller Enabled Enabled Disabled SMBus Controller GbE Controller Enabled Enabled Disabled GbE Controller Wake on Lan from S5 Enabled Enabled Disabled GbE control PME in S5 SLP_S4 Assertion Stre Enabled Enabled Disabled SLP_S4 Assertion Stretch SLP_S4 Assertion Wid 4 5 Seconds Select a minimum assertion width of the SLP_S4 si...

Page 89: ...ces Onboard SAS Oprom Disabled Enable Disable onboard SAS Option rom if Launch Storage OpROM is enabled Onboard SATA RAID Opr Enabled Enable Disable onboard SATA RAID Option rom if Launch Storage OpROM is enabled High Precision Timer Enabled Enable Disable the High Precision Event Timer USB Configuration Submenu Advanced USB Configuration ...

Page 90: ... 5 19 Server Mgmt Configuration Feature Default Description BMC Support Enabled Enable Disable interfaces to communicate with the BMC OS Watchdog Timer Disabled If enabled starts a BIOS timer which can only be shut off by Intel Management Software after the OS loads Helps determine that the OS successfully loaded or follows the OS Boot OS Wtd Timer Timeout 10 minutes Configure the length of the OS...

Page 91: ...application Figure 5 20 Boot Configuration BMC self test log Submenu Logs the report returned by the BMC self test command System Event Log Submenu Press Enter to change the SEL event log configuration View FRU information Display Only Press Enter to view FRU information Feature Default Description Setup Prompt Timeout 1 Number of seconds to wait for setup activation key 65535 0xFFFF means indefin...

Page 92: ...Note Fast Boot Disabled Enables or disables boot with an initialization of a minimal set of devices required to launch active boot option Has no effect for BBS boot option CSM16 Module Version Display Only Shows the current version in use Option ROM Messages Force BIOS Set display mode for Option ROM Interrupt 19 Capture Immediate Enabled Allows Option ROMs to trap Int 19 Boot Option User Defined ...

Page 93: ...figuration results as User Defaults Users can select Save as User Defaults to record all changes which had been made in previous pages as the default setting for further use Figure 5 22 Save Exit Configuration Feature Description Save Changes and Exit Exit system setup after saving the changes Discard Changes and Exit Exit system setup without saving any changes Save Changes and Reset Reset system...

Page 94: ...nfiguration Restore Defaults Restore Load Default values for all the setup options Save as User Defaults Save the changes done so far as User Defaults Restores User Defaults Restore the User Defaults to all the setup options ...

Page 95: ...Chapter 6 Firmware Upgrade This chapter describes how to update the IPMC FW FPGA and BIOS for the MIC 5332 ...

Page 96: ...ning descriptions reference IPMITool HPM 1 provides a way to upgrade firmware via different interfaces on ATCA platforms LAN interface RMCP KCS on board payload interface OS support needed or IPMB bridged via the Shelf Manager The following upgrade processes use KCS as interface over which upgrades are delivered to the IPMC Using LAN or IPMB is similar only the interface parameter in the related I...

Page 97: ...alidating firmware image integrity OK Performing preparation stage Target Product ID 21298 Target Manufacturer ID 10297 OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 0 50 100 Time Size 1 Id IPMC 0 45 0 44 0 46 00 51 4bf31 Firmware upgrade procedure successful ...

Page 98: ...d 2 red OOS and green payload LED are flashing This procedure needs around 30 seconds to finalize the update It will need an IPMC reset to complete the FW upgrade The user can detect an upgrade failure with an Integrity sensor event 6 4 FPGA Upgrade 6 4 1 Upload new FPGA image Type IPMItool HPM 1 upgrade command and select the new IPMC firmware image root localhost ipmitool hpm activate PICMG HPM ...

Page 99: ...image integrity OK Performing preparation stage Target Product ID 21298 Target Manufacturer ID 10297 OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 0 50 100 Time Size 2 5332 FPGA 2 13 2 12 2 14 01 08 6eea0 Component requires Payload Cold Reset Firmware upgrade procedure successful ...

Page 100: ...h different ways If the user is working on the OS via KCS a linux reboot poweroff or halt will activate the new FPGA image If the user accesses the BMC through other interfaces LAN IPMB a deactivation and activation cycle is needed in order to update the FPGA During the FPGA update the front panel FRU LED s 1 and 2 red OOS and green payload LED are flashing This procedure needs around 60 seconds t...

Page 101: ...should be the version of the upload file 6 5 BIOS Upgrade root localhost ipmitool hpm check PICMG HPM 1 Upgrade Agent 1 0 2 Target Information Device Id 0x22 Device Revision 0x81 Product Id 0x5332 Manufacturer Id 0x2839 Advantech ID Name Versions Active Backup 0 5332 BL 0 45 1 5332 IPMC 0 45 0 45 2 5332 FPGA 2 14 2 13 3 5332 BIOS 0 23 0 23 4 5332 NVRAM 0 04 Component requires Payload Cold Reset ...

Page 102: ...llowing HPM 1 command root localhost ipmitool hpm upgrade mic5332_standard_hpm_bios_00_23 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Target Product ID 21298 Target Manufacturer ID 10297 OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 0 50 100 Time Size 3 Id BIOS 0 21 0 21 0 23 17 43 7c000c Com...

Page 103: ...ccesses the BMC through other interfaces LAN IPMB a deactivation and activation cycle is needed in order to update the FPGA 6 5 4 Verify successful Upgrade To verify the update process the hpm check of the IPMItool can be used again Now the BIOS Backup Version should be the former active version and the active version should be the version of the upload file Component requires Payload Cold Reset r...

Page 104: ...time Each of these settings can be set to active at any time and will be copied to the active BIOS flash at the next OS boot 6 6 1 Select Upgrade Section optional As described above the IPMC provides multiple upgrade sections for different NVRAM sections OEM commands are used to select the upload and activation setting from the different BIOS setting sections in the external flash root localhost i...

Page 105: ... root localhost ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x01 section ...

Page 106: ...cted NVRAM section root localhost ipmitool raw 0x2E 0x40 0x39 0x28 0x00 0x03 0x02 section root localhost ipmitool hpm upgrade mic5332_standard_hpm_bios_00_05 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Target Product ID 21298 Target Manufacturer ID 10297 OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Back...

Page 107: ...performed through different ways If the user is working on the OS via KCS a linux reboot poweroff or halt will activate the new NVRAM image If the user accesses the BMC through other interfaces LAN IPMB a deactivation and activation cycle is needed in order to update the NVRAM Component requires Payload Cold Reset ...

Page 108: ...Appendix A IPMI PICMG Command Subset Supported by IPMC ...

Page 109: ...I Spec Ref NetFn CMD IPMI PICMG3 0 AMC2 0 Requirement Set BMC Global Enables 22 1 App 2Eh Optional Mandatory Get BMC Global Enables 22 2 App 2Fh Optional Mandatory Clear Message Flags 22 3 App 30h Optional Mandatory Get Message Flags 22 4 App 31h Optional Mandatory Get Message 22 6 App 33h Optional Mandatory Send Message 22 7 App 34h Optional Mandatory Get System GUID 22 14 App 37h Optional Get Ch...

Page 110: ...ds Command IPMI Spec Ref NetFn CMD IPMI PICMG3 0 AMC2 0 Requirement Set Event Receiver 29 1 S E 00h Mandatory Get Event Receiver 29 2 S E 01h Mandatory Platform Event a k a Event Message 23 3 S E 02h Mandatory Sensor Device Commands Command IPMI Spec Ref NetFn CMD IPMI PICMG3 0 AMC2 0 Requirement Get Device SDR Info 35 2 S E 20h Mandatory Get Device SDR 35 3 S E 21h Mandatory Reserve Device SDR Re...

Page 111: ...ry 31 6 Storage 44h Mandatory Clear SEL 31 9 Storage 47h Mandatory Get SEL Time 31 10 Storage 48h Mandatory Set SEL Time 31 11 Storage 49h Mandatory LAN Device Commands Command IPMI Spec Ref NetFn CMD IPMI PICMG3 0 AMC2 0 Requirement Set LAN Configuration Parameters 23 1 Transport 01h Optional Mandatory Get LAN Configuration Parameters 23 2 Transport 02h Optional Mandatory Serial Modem Device Comm...

Page 112: ...ICMG 0Fh Optional Mandatory Compute Power Properties 3 82 PICMG 10h Mandatory Set Power Level 3 84 PICMG 11h Mandatory Get Power Level 3 83 PICMG 12h Mandatory Get IPMB Link Info 3 68 PICMG 18h Optional Mandatory FRU Control Capabilities 3 26 PICMG 1Eh Mandatory HPM 1 Upgrade Commands Command HPM 1 Table NetFn CMD IPMI PICMG3 0 AMC2 0 Requirement Get target upgrade capabilities 3 3 PICMG 2Eh Manda...

Page 113: ...MI OEM commands listed in below table Command LUN NetFn CMD Store Configuration Settings 00h 2Eh 2Fh 40h Read Configuration Settings 00h 2Eh 2Fh 41h Read Port 80 BIOS POST Code 00h 2Eh 2Fh 80h Clear CMOS 00h 2Eh 2Fh 81h Read MAC Address 00h 2Eh 2Fh E2h Load Default Configuration 00h 2Eh 2Fh F2h A 1 IPMItool raw command To be able to use the Advantech OEM commands with the open source IPMItool user...

Page 114: ...to the selected LAN controller interface users may need to configure each single LAN controller channel port as dedicated NC SI interface to the BMC Additional OEM commands for the configuration of the NC SI LAN controller channel selection and priority are provided to allow a flexible configuration LAN channel selection priority setting list 0 The first channel that links up gets the NC SI connec...

Page 115: ...e configured in some ways This is done inside the FPGA with the help of an UART MUX refer to chapter x x x UART MUX The BMC provides OEM commands to configure these UARTs via IPMI Following COM1 COM2 port settings are available Caution Verify note below about the UART dependency COM interfaces Port Interface 0x00 COM1 0x01 COM2 Table 1 COM interfaces COM1 MUX Setting Connection 0x00 no interface c...

Page 116: ...te The COM1 UART is the main interface with higher priority There is an important dependency between COM1 and COM2 UARTs users should know and aware of The COM2 MUX can ONLY be used if the COM1 MUX is set to SOL 0x01 If the COM1 MUX has any other settings than SOL COM2 is permanently fixed to SOL and the COM2 MUX OEM command setting is ignored Read COM port UART MUX setting Response Change COM por...

Page 117: ...jumper plug and re plug Response A 5 MAC Address Mirroring OEM command The blade LAN Controller MAC addresses will also be stored in the FRU EEPROM making the MAC s available even if the payload is not powered The MIC 5332 board is equipped with 7 MAC addresses in total Please find below the used order in the FRU EEPROM Internal Use Area MAC Number LAN Interface 0 Fabric interface 1 1 Fabric inter...

Page 118: ...mand Several configurations settings are provided by the IPMC verify chapter x x x Configuration Setting OEM commands To reset all of them to their default values a single OEM command is available to perform this with only one IPMI command Response 39 28 00 ipmitool raw 0x2e 0xF2 0x39 0x28 0x00 39 28 00 MAC Address ipmitool raw 0x2e 0xe2 0x39 0x28 0x00 MAC Number ...

Page 119: ...SCL_A IPMB0 A clock 14 SDA_A IPMB0 A data 15 SCL_B IPMB0 B clock 16 SDA_B IPMB0 B data 17 MT1_TIP No connected 18 MT2_TIP No connected 19 RING_A No connected 20 RING_B No connected 21 MT1_RING No connected 22 MT2_RING No connected 23 RRTN_A No connected 24 RRTN_B No connected 25 SHELF_GND Connect to shelf ground 26 LOGIC_GND Connect to logic ground 27 ENABLE_B Enable 48V_B power 28 VRTN_A 48V retu...

Page 120: ...33 48V_A 48V input feed A 34 48V_B 48V input feed B ...

Page 121: ...Rx4 UP Rx4 UP N C N C N C N C 3 Tx2 UP Tx2 UP Rx2 UP Rx2 UP Tx3 UP Tx3 UP Rx3 UP Rx3 UP 4 Tx0 UP Tx0 UP Rx0 UP Rx0 UP Tx1 UP Tx1 UP Rx1 UP Rx1 UP 5 N C N C N C N C N C N C N C N C 6 N C N C N C N C N C N C N C N C 7 N C N C N C N C N C N C N C N C 8 N C N C N C N C N C N C N C N C 9 N C N C N C N C N C N C N C N C 10 N C N C N C N C N C N C N C N C ...

Page 122: ...C N C N C N C N C N C N C N C 6 N C N C N C N C N C N C N C N C 7 FI_CH4 Tx2 FI_CH4 Tx2 FI_CH4 Rx2 FI_CH4 Rx2 FI_CH4 Tx3 FI_CH4 Tx3 FI_CH4 Rx3 FI_CH4 Rx3 8 FI_CH4 Tx0 FI_CH4 Tx0 FI_CH4 Rx0 FI_CH4 Rx0 FI_CH4 Tx1 FI_CH4 Tx1 FI_CH4 Rx1 FI_CH4 Rx1 9 FI_CH3 Tx2 FI_CH3 Tx2 FI_CH3 Rx2 FI_CH3 Rx2 FI_CH3 Tx3 FI_CH3 Tx3 FI_CH3 Rx3 FI_CH3 Rx3 10 FI_CH3 Tx0 FI_CH3 Tx0 FI_CH3 Rx0 FI_CH3 Rx0 FI_CH3 Tx1 FI_CH3 T...

Page 123: ... Tx2 FI_CH1 Tx2 FI_CH1 Rx2 FI_CH1 Rx2 FI_CH1 Tx3 FI_CH1 Tx3 FI_CH1 Rx3 FI_CH1 Rx3 4 FI_CH1 Tx0 FI_CH1 Tx0 FI_CH1 Rx0 FI_CH1 Rx0 FI_CH1 Tx1 FI_CH1 Tx1 FI_CH1 Rx1 FI_CH1 Rx1 5 BI_CH1 DA BI_CH1 DA BI_CH1 DB BI_CH1 DB BI_CH1 DC BI_CH1 DC BI_CH1 DD BI_CH1 DD 6 BI_CH2 DA BI_CH2 DA BI_CH2 DB BI_CH2 DB BI_CH2 DC BI_CH2 DC BI_CH2 DD BI_CH2 DD 7 N C N C N C N C N C N C N C N C 8 N C N C N C N C N C N C N C ...

Page 124: ...P RTM_IPMBL 7 RTM_MMC_ RTM_PERST0 RTM_ENABLE RTM_PS RTM_LINK 6 not connected not connected RTM_USB1 RTM_USB0 5 not connected not connected 4 RTM_UART1 RTM_UART0 3 not connected RTM_PCIE2_CLK RTM_PCIE1_CLK RTM_PCIE0_CLK 2 PEx4_2 RTM_PE4 0_3 PEx4_2 RTM_PE4 0_2 1 PEx4_2 RTM_PE4 0_1 PEx4_2 RTM_PE4 0_0 ...

Page 125: ...t J34 Pin Row M A 8 PEx16_1 RTM_PE16 1_0 RX PEx16_1 RTM_PE16 1_4 RX PEx16_1 RTM_PE16 1_0 TX PEx16_1 RTM_PE16 1_4 TX 7 PEx16_1 RTM_PE16 1_0 RX PEx16_1 RTM_PE16 1_12 RX PEx16_1 RTM_PE16 1_8 TX PEx16_1 RTM_PE16 1_12 TX 6 PEx16_1 RTM_PE16 1_1 RX PEx16_1 RTM_PE16 1_5 RX PEx16_1 RTM_PE16 1_1 TX PEx16_1 RTM_PE16 1_5 TX 5 PEx16_1 RTM_PE16 1_2 RX PEx16_1 RTM_PE16 1_13 RX PEx16_1 RTM_PE16 1_9 TX PEx16_1 RTM...

Page 126: ...X PEx16_1 RTM_PE16 1_10 TX PEx16_1 RTM_PE16 1_14 TX 2 PEx16_1 RTM_PE16 1_3 RX PEx16_1 RTM_PE16 1_7 RX PEx16_1 RTM_PE16 1_3 TX PEx16_1 RTM_PE16 1_7 TX 1 PEx16_1 RTM_PE16 1_11 RX PEx16_1 RTM_PE16 1_15 RX PEx16_1 RTM_PE16 1_11 TX PEx16_1 RTM_PE16 1_15 TX ...

Page 127: ... NC GND FI4_RX2_N GND PCIE1_TX6_N 16 NC GND FI4_RX3_P GND PCIE1_TX7_P GND 17 NC GND FI4_RX3_N GND PCIE1_TX7_N GND 18 GND NC GND PCIE0_RX0_P GND PCIE1_RX0_P 19 GND NC GND PCIE0_RX0_N GND PCIE1_RX0_N 20 NC GND PCIE0_RX1_P GND PCIE1_RX1_P GND 21 NC GND PCIE0_RX1_N GND PCIE1_RX1_N GND 22 GND NC GND PCIE0_RX2_P GND PCIE1_RX2_P 23 GND NC GND PCIE0_RX2_N GND PCIE1_RX2_N 24 NC GND PCIE0_RX3_P GND PCIE1_RX...

Page 128: ... GND FI3_TX0_P 3 GND NC GND FI3_TX0_N 4 NC GND FI3_TX1_P GND 5 NC GND FI3_TX1_N GND 6 GND NC GND FI3_TX2_P 7 GND NC GND FI3_TX2_N 8 NC GND FI3_TX3_P GND 9 NC GND FI3_TX3_N GND 10 GND NC GND FI4_TX0_P 11 GND NC GND FI4_TX0_N 12 NC GND FI4_TX1_P GND 13 NC GND FI4_TX1_N GND 14 GND NC GND FI4_TX2_P 15 GND NC GND FI4_TX2_N 16 NC GND FI4_TX3_P GND 17 NC GND FI4_TX3_N GND 18 GND NC GND PCIE0_TX0_P 19 GND...

Page 129: ...30 GND FPGA_GPIO_P4 GND PCIE0_TX6_P 31 GND FPGA_GPIO_N4 GND PCIE0_TX6_N 32 FPGA_GPIO_P6 GND PCIE0_TX7_P GND 33 FPGA_GPIO_N6 GND PCIE0_TX7_N GND 34 GND NC GND NC 35 GND NC GND NC 36 NC GND NC GND 37 NC GND NC NC 38 GND USB2_DP GND FI4_LED_HS 39 USB1_DP USB2_DN 12V FI4_LED_LS 40 USB1_DN GND 12V GND HPC only LPC ...

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