Advantech IPPC-6172A Series, User Manual

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IPPC-6172A User Manual vi
5.1 BIOS Setup Program .............................................................................. 24
5.1.1
Legend Box................................................................................. 24
5.1.2 List Box ....................................................................................... 25
5.1.3 Sub-menu ................................................................................... 25
5.2 Main Setup.............................................................................................. 25
5.3 Advanced BIOS Setup ............................................................................ 26
5.3.1
Super I/O Configuration .............................................................. 29
5.3.2 ACPI Configuration ..................................................................... 32
5.3.3 AHCI Configuration..................................................................... 33
5.3.4 APM Configuration...................................................................... 34
5.3.5 Configure intel AT-d Parameters ................................................ 35
5.3.6 Intel AMT Configuration .............................................................. 36
5.3.7 Intel VT-d Configuration.............................................................. 37
5.3.8 Trusted Computing ..................................................................... 38
5.4 Advanced PCI/PnP Settings ................................................................... 39
5.5 Boot Setting Configuration ...................................................................... 41
5.6 Security Setup......................................................................................... 44
5.7 Chipset Setup ......................................................................................... 45
5.7.1
North Bridge Configuration ......................................................... 45
5.7.2 South Bridge Configuration......................................................... 47
5.8 Exit Menu ................................................................................................ 48
Appendix A I/O & Connector Pin Assignments .. 51
A.1 CN1, CN2 LVDS ..................................................................................... 52
Appendix B System Assignments ........................ 61
B.1 System I/O Ports..................................................................................... 62
Table B.1: System I/O Ports ...................................................... 62
B.2 DMA Channel Assignments .................................................................... 62
Table B.2: DMA Channel Assignments ..................................... 62
B.3 Interrupt Assignments ............................................................................. 63
Table B.3: Interrupt Assignments .............................................. 63
B.4 1st MB Memory Map............................................................................... 63
Table B.4: 1st MB Memory Map ................................................ 63
B.5 PCI Bus Map........................................................................................... 63
Table B.5: PCI Bus Map ............................................................ 63
Appendix C Watchdog Timer ................................ 65
C.1 Overview ................................................................................................. 66
C.2 Watchdog Timer Programming ............................................................... 66