Advantech EKI-8500 Series, User Manual

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EKI-8500 Series User Manual 65
4.3.6 PTP
This function allows you to configure and inspect the current PTP clock settings.
1. Navigate to Configuration and click PTP .
The PTP Clock Configuration page displays.
Figure 4.39 PTP Clock Configuration
The following table describes the items in the PTP Clock Configuration page.
Paths Displays the latent error detection paths.
Reset Period Displays the latent error detection reset period.
Oper Displays the operational state of FRER instance.
Warnings Displays the operational warnings of FRER instance.
Latent Error Displays any detected latent errors.
Configuration
Buttons
Click to modify an entry. Options:

Edit: Edits the FRER instance.

Delete: Deletes the FRER instance.

Add: Adds new FRER instance.
Refresh Click Refresh to refresh the page immediately.
Item Description
Item Description
One_PPS_Mode Click the drop-down menu to select the One_pps_mode configuration.
The following values are possible:

Output: Enable the 1 pps clock output

Input: Enable the 1 pps clock input

Disable: Disable the 1 pps clock in/out-put
External Enable Click the drop-down menu to configure the External Clock output.
The following values are possible:
 True: Enable the external clock output
 False: Disable the external clock output
Adjust Method Click the drop-down menu to configure the Frequency adjustment
configuration.

LTC: Select Local Time Counter (LTC) frequency control

Single: Select SyncE DPLL frequency control, if allowed by
SyncE

Independent: Select an oscillator independent of SyncE for
frequency control, if supported by the HW

Common: Select second DPLL for PTP, Both DPLL have the
same (SyncE recovered) clock.

Auto: AUTO Select clock control, based on PTP profile and
available HW resources.