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PCM-3718H/3718HG User's Manual
DMA channel and timer clock selection (JP1)
The PCM-3718H/3718HG supports DMA data transfer. The bottom
pins of JP1 provide selection of DMA channel 1 or 3, as shown in the
following figure.
The upper jumper of JP1 controls the input clock frequency for the
8254 programmable clock/timer of the module. You have two
choices: 10MHz and 1MHz. This lets you generate pacer output
frequencies from 2.5 MHz to 0.00023 Hz (71 minutes/pulse).
The following equation gives the pacer rate:
Pacer rate = Fclk / ( Div1 * Div2 )
(Fclk, 1MHz or 10MHz, is set by JP1 as illustrated above. Div1 and
Div2 are dividers set in counter 1 and counter 2 in the Intel 8254
counter. See page 51 for more information on the counter/timer
applications).
Channel configuration, S. E. or diff. (JP2)
The PCM-3718H/3718HG offers 16 single-ended or eight differential
analog input channels. Jumper JP2 sets the analog input channels as
16 single-ended or 8 differential inputs as below:
1 0 M
1 M
D M 1
D M 3
Channel 1
1 0 M
1 M
D M 1
D M 3
Channel 3 (default)
10M
1M
DM1
DM3
10 MHz
10M
1M
DM1
DM3
1 MHz (default)
S/E
DIFF
16 S.E. inputs
S/E
DIFF
Eight differential inputs (default)
Summary of Contents for 3718HG
Page 1: ...PCM 3718H 3718HG PC 104 12 bit DAS Module with Programmable Gain User s manual ...
Page 2: ......
Page 5: ...1 General Information CHAPT ER ...
Page 13: ...2 Installation CHAPT ER ...
Page 21: ...3 Signal Connections CHAPT ER ...
Page 26: ...22 PCM 3718H 3718HG User s Manual ...
Page 27: ...4 Register Structure and Format CHAPT ER ...
Page 38: ...34 PCM 3718H 3718HG User s Manual ...
Page 39: ...5 A D Conversion CHAPT ER ...
Page 45: ...6 Digital Input Output CHAPT ER ...
Page 47: ...7 Programmable Pacer CHAPT ER ...
Page 57: ...8 Direct Memory Access Operation CHAPT ER ...
Page 60: ...56 PCM 3718H 3718HG User s Manual ...
Page 61: ...9 Calibration CHAPT ER ...
Page 64: ...60 PCM 3718H 3718HG User s Manual ...