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4
PCM-3718H/3718HG User's Manual
•
Differential nonlinearity error: ±1 LSB
•
Input impedance: 1G
Ω
•
Trigger mode: Software, pacer or external trigger
•
External trigger: TTL compatible
Digital Input/ Output:
•
Channels: two 8-bit
•
Level: TTL compatible
•
Input voltage:
Logic 0: 0.8 V max.
Logic 1: 2.0 V min.
•
Output voltage:
Logic 0: 0.33 V max. @ 6 mA (sink)
Logic 1: 3.84 V min. @ 6 mA (source)
Programmable pacer:
•
Device: Intel 8254 or equivalent
•
Counters: 3 channels, 16-bit.
Counter 1 and Counter 2 are permanently configured as a 32-bit
programmable pacer. Counter 0 is reserved for future development.
•
Time base: (for Counter 1’s clock input)
10 MHz or 1 MHz, jumper selectable.
General:
•
Power consumption: +5V
DC
@ 180mA (Typical)
+5V
DC
@ 400mA (Max.)
•
Digital I/O connector: 20-pin post headers for I/O connection.
•
Analog input connector: 20-pin post headers for I/O connection.
•
Operating temperature: 0 to +60°C (refer to IEC 68-2-1, 2)
•
Storage temperature: -20 to +70°C
•
Operating humidity: 5 to 95% non-condensing
(refer to IEC 68-2-3)
•
MTBF: over 235,346 hrs @ 25°C, ground, fix environment
Summary of Contents for 3718HG
Page 1: ...PCM 3718H 3718HG PC 104 12 bit DAS Module with Programmable Gain User s manual ...
Page 2: ......
Page 5: ...1 General Information CHAPT ER ...
Page 13: ...2 Installation CHAPT ER ...
Page 21: ...3 Signal Connections CHAPT ER ...
Page 26: ...22 PCM 3718H 3718HG User s Manual ...
Page 27: ...4 Register Structure and Format CHAPT ER ...
Page 38: ...34 PCM 3718H 3718HG User s Manual ...
Page 39: ...5 A D Conversion CHAPT ER ...
Page 45: ...6 Digital Input Output CHAPT ER ...
Page 47: ...7 Programmable Pacer CHAPT ER ...
Page 57: ...8 Direct Memory Access Operation CHAPT ER ...
Page 60: ...56 PCM 3718H 3718HG User s Manual ...
Page 61: ...9 Calibration CHAPT ER ...
Page 64: ...60 PCM 3718H 3718HG User s Manual ...