10. Watchdog timer
A96G140/A96G148/A96A148 User’s manual
90
WDTDR (Watch Dog Timer Data Register: Write Case): 8EH
7
6
5
4
3
2
1
0
WDTDR7
WDTDR 6
WDTDR 5
WDTDR 4
WDTDR 3
WDTDR 2
WDTDR 1
WDTDR 0
W
W
W
W
W
W
W
W
Initial value: FFH
WDTDR[7:0]
Set a period
WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1)
NOTE:
Do not write
“0” in the WDTDR register.
WDTCR (Watch Dog Timer Control Register): 8DH
7
6
5
4
3
2
1
0
WDTEN
WDTRSON
WDTCL
–
–
–
WDTCK
WDTIFR
R/W
R/W
R/W
–
–
–
R/W
R/W
Initial value: 00H
WDTEN
Control WDT Operation
0
Disable
1
Enable
WDTRSON
Control WDT RESET Operation
0
Free Running 8-bit timer
1
Watch Dog Timer RESET ON
WDTCL
Clear WDT Counter
0
Free Run
1
Clear WDT Counter (auto clear after 1 Cycle)
WDTCK
Control WDT Clock Selection Bit
0
BIT overflow for WDT clock
1
BIT overflow/8 for WDT clock
WDTIFR
When WDT Interrupt occurs, this bit becomes
‘1’. For clearing bit, write
‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has no effect.
0
WDT Interrupt no generation
1
WDT Interrupt generation