A96G140/A96G148/A96A148 User’s manual
15. USI
183
USInDR (USIn Data Register: For UART, SPI, and I2C mode): E5H/F5H, n = 0, 1
7
6
5
4
3
2
1
0
USInDR7
USInDR 6
USInDR 5
USInDR 4
USInDR 3
USInDR 2
USInDR 1
USInDR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
USInDR[7:0]
The USIn transmit buffer and receive buffer share the same I/O
address with this DATA register. The transmit data buffer is the
destination for data written to the USInDR register. Reading the
USInDR register returns the contents of the receive buffer.
Write to this register only when the DREn flag is set. In SPI master
mode, the SCK clock is generated when data are written to this
register.
USInSDHR (USInSDA Hold Time Register: For I2C mode): E4H/F4H, n = 0, 1
7
6
5
4
3
2
1
0
USInSDHR7
USInSDHR6
USInSDHR5
USInSDHR 4
USInSDHR 3
USInSDHR 2
USInSDHR 1
USInSDHR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 01H
USInSDHR[7:0]
The register is used to control SDAn output timing from the falling
edge of SCI in I2C mode.
NOTES:
1.
That SDAn is changed after t
SCLK
X (U2), in
master SDAn change in the middle of SCLn.
2.
In slave mode, configure this register regarding the
frequency of SCLn from master.
3.
The SDAn is changed after t
SCLK
X (U2) in
master mode. So, to insure operation in slave mode, the
value t
SCLK
X (U2) must be smaller than the
period of SCL.
USInSCHR (USInSCL High Period Register: For I2C mode): E7H/F7H, n = 0, 1
7
6
5
4
3
2
1
0
USInSCHR7
USInSCHR6
USInSCHR5
USInSCHR 4
USInSCHR 3
USInSCHR 2
USInSCHR 1
USInSCHR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 3FH
USInSCHR[7:0]
This register defines the high period of SCLn when it operates in
I2C master mode.
The base clock is SCLK, the system clock, and the period is
calculated by the formula: t
SCLK
X (4 X US2) where
t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
f
I2C
=
t
SCLK
X (4 X (US USInSCHR) + 4)
1