I.L. 40-385.5
5-1
All currents and voltages for MDAR (REL-300) sys-
tem, as shown in Figure 3, are sampled and con-
verted into digital quantities and input to the micro-
processor where all signal processing takes place.
The system timing and software design is based on
the power line frequency. The analog inputs are con-
tinuously sampled 8 times per power line cycle.
The first activity of each sample period is the sam-
pling of the seven analog inputs and computation of
the Fourier and sum of squares components. The
remainder of the activity for each sample period is
determined by the mode of operation (background or
fault mode) and the number of the sample period (0
or 7).
MDAR (REL-300) has an internal mode of operation
which is generally controlled by the status of the pro-
tected line. There are three normal software modes:
initialization Mode is maintained for one cycle after
the MDAR 9REL-300) relay is energized or reset;
Background Mode is the normal operating mode;
Fault Mode handles high-speed tripping. Calibration
Mode is the fourth mode of operation which is
entered after Initialization Mode if JMP6 on the pro-
cessor module is installed.
5.1
FLOW CHART
The MDAR (REL-300) system software is written in
80C196 Assembly Language.
The software flow is based on the sampling rate and
the 60 Hz line frequency. There are eight states per
cycle, which correspond to the eight sample per
cycle sampling rate. Movement from state to state is
controlled by a timer. The timer is loaded with a state
time at the beginning of the state. The code executed
within a state should be completed before the timer
expires. The software then waits for the timer to time
out.
Figure 7 shows a simplified flowchart for the relaying
programs in MDAR (REL-300). All programs are
included in a loop, as shown, which the processor
repeats eight times per power cycle. Most functions
are performed all of the time in the background
mode, as shown.
An important detail not shown in Figure 7 is that
many of the checks are broken into small parcels, so
that the whole complement of tasks is performed
over an one-cycle period, eight passes through the
loop. some of the checks are done more than once
each cycle.
During non-fault operation, the programs follow the
Background Mode loop. The processor uses its
spare time to check its hardware, service the opera-
tor panel and check for a disturbance in voltage or
current which indicates a possible fault. If a distur-
bance is seen, the programs switch to fault mode, for
several power cycles or longer, to perform phase and
ground unit checks for each zone and function.
The instantaneous voltage and current sampling val-
ues are converted to RMS and phasor values using a
Fourier notch-filter algorithm. an additional dc offset
correction algorithm reduces overreach errors from
decaying exponential transients.
5.2
INITIALIZAITON
The initialization routine is executed upon power up
of the MDAR (REL-300) relay. All microcomputer
input and output pins and internal control registers
are initialized. The system self-checks are per-
formed. If a failure is detected, the failure alarm relay
is de-energized and the failure code is displayed. The
system remains in Initialization Mode for the first
cycle of data collection. No tripping occurs during this
cycle.
Upon successful completion of the initialization rou-
tine, the program jumps to the initial cycle at a sam-
pling routine where input signal processing begins.
5.3
BACKGROUND MODE
MDAR (REL-300) detects faults by direct computa-
tion (not analog). The relay normally operates in a
Background Mode when no fault is present.
The input currents and voltages are sampled and
processed to compute RMS and phasor values. The
sum of squares and the sums of the Fourier coeffi-
cients are updated each sample using information
from the previous seven samples to provide a full
cycle of data. The RMS and the phasor values of the
Section 5. DESCRIPTION OF SOFTWARE
