I.L. 40-385.5
10-7
features:
(1) SPT/SRI on first fault.
(2) 3PT/RB if reclosing on a permanent
fault.
(3) 3PT/RB if second phase(s) fault during
single-phasing.
(4) 3PT on a preset time limit (62T) if the
system fails to reclose.
(5) Trip/RI mode selection.
The functional display TTYP settings, OFF/1PR/2PR/
3PR/SPR/SR3R provide the following operating
mode selections:
TTYP TRIPPING MODE
RECLOSING INITIATE
OFF
3PT on all faults
No reclosing
1PR
3PT on all faults
RI2 on ØG faults only
2PR
3PT on all faults
RI2 on ØG/ØØØ/ØØG faults
3PR
3PT on all faults
RI2 on all faults
SPR
SPT on ØG faults,
RI1 on ØG faults only,
3PT on others
no reclosing on others
SR3R
SPT on ØG fault,
RI1 on ØG faults,
3PT on others
RI2 on others
where RI1/RI2 are separated output contacts for
external application.
The SPT logic as shown in Figure 38 is proposed by
EPRI/China. Its design is based on the power system
operation practices and experiences in China.
The pole-disagreement circuit does not use 52a/52b
contacts. It uses the MDAR (REL-300) trip signals
TRSLA, TRSLB, TRSLC and the resetting of fault
phase current signals I
A
, I
B
, I
C
for identifying the
pole-disagreement condition.
Refer to Figure 38, the pole-disagreement signals
XA1, XB1, XC1 will be used for disabling the faulted
phase impedance units, Z1G/Z2G/Z3G /PLTG
(includes FDOG/I
oM
), for 1 to 6 seconds in 1.0 sec-
ond steps (based on the SPTT timer setting) once
the faulted phase has been tripped.
Provision for connecting the external signals XTRIPA,
XTRIPB, XTRIPC for initiating the MDAR (REL-300)
pole-disagreement logic if breaker is operated by
other SPT protection. This logic includes OR-78D,
OR-78E, and OR-78F.
For SPT mode, the TTYP setting should be selected
to either SPR or SR3R position. The SPT logic pro-
vides the following functions:
10.2.4 Single-pole-trip (SPT) and single-pole-
reclosing initiate (RI1) on ØG faults.
Refer to Figure 38, for example, on an AG-fault, the
Ø
A ground distance ZA and I
oM
units operate. This
provides an output signal from OR-2. 3-pole trip
(3PT) path of AND-68 is inhibited by the presence of
no 3PTN signal to AND-68, since TTYP is set at
either SPR or SR3R (refer to system drawing
2687F04 sheet 1). SPT
Ø
A occurs via AND-69
because the faulted phase selector AG-unit picks up.
Single-pole-reclosing initiate unit RI1 picks up via
AND-85 (Figure 24) after the faulted pole trip circuit
has been energized.
The FDOG path is for the detectionof single phase
with high resistance to ground fault. for the phase-
phase-ground fault condition this path may be
blocked if the setting of TTYP=SRP or SR3R
because the phase selector shows a fault type of
phase-phase fault and it expects the Z1P or PLTP trip
only. (Refer to Figure 38 gate AND 48E.)
10.2.5 Three-pole-trip and reclosing block (RB) on
unsuccessful reclosing.
On an unsuccessful single-pole reclose, the reclose-
on-fault, ROF signal, will trip 3-pole by the output sig-
nal from AND-75D. ROF is identified by the combined
information of fault current and pole-disagreement
signals, i.e. XA1/IAM, XB1/IBM, XC1/ICM and I
oM
.
This logic includes AND-75A, AND-75B, AND-75C,
OR-75, AND-75D and the 60/0 timer in Figure 38.
ROF trip will also initiate RB and with CIF target.
10.2.6 Three-pole-trip and reclosing block on
“sound phase fault” (SPF) during single-
phasing.
Once the SPT has been performed, the pole dis-
agreement circuit sets the X2 signal via OR-75F. SPF
trips 3-pole by the output signal of S3PT via AND-77
(Figure 38) if a sound phase(s) fault occurs during
single-phasing. Reclosing block RB will be initiated
by S3PT signal and via logic OR-61, OR-86A and
AND-86B in Figure 24.
10.2.7 Three-pole-trip and reclosing block when the
single phasing limit timer is timed out.
In case of malfunction on the external reclosing
scheme, three-pole trip and RB will be performed by
