I.L. 40-385.5
12-1
12.1 SELECTABLE LOSS-OF-LOAD ACCELER-
ATED TRIP (LLT).
The load-loss speedup Zone-2 trip logic senses
remote 3-pole clearing on all faults except
3
∆
to com-
plement or substitute for the action of the pilot chan-
nel, to speed up trip at the slow terminal.
12.2 PILOT GROUND TRIP
Pilot Ground Trip is more dependable on high Rf
faults because it is supplemented with FDOG/IoM
(refer to Figure 34). Trip delay is controlled by the set-
ting of the FDGT timer (Forward Directional Overcur-
rent Ground Timer). The range of this timer is 0 to 15
cycles in 1 cycle steps and with BLK step for dis-
abling this trip function if required. The pilot distance
unit PLTG is always active and has the priority for
tripping, therefore, practically, the FDGT timer should
be set to 3 cycles or longer for security reason.
12.3 THE REVERSE-BLOCK FEATURE
The Reverse-Block feature makes the high speed trip
ground unit Z1G more secure on unequal pole clear-
ing on reverse faults, as shown in Figure 36.
12.4 PILOT GROUND
Pilot ground is more secure on POTT/unblocking
schemes on some special power system conditions,
such as shown in Figure 35.
When a
ØØ
G fault is on the paralleled line section,
due to the system condition, fault current flowing in
the protected line would be I1+I2 from A to B, and Io
from B to A.
The operation of pilot distance relays would include a
phase relay at A and a ground relay at B. The result
would be erroneous directional comparison of an
external fault as an “internal” one. The POTT and
unblocking scheme will incorrectly trip out the pro-
tected line.
MDAR (REL-300) pilot ground unit(s), PLTG/FDOG,
is supervised by the reverse looking ground unit
RDOG. The “reverse-block” logic is as shown in Fig-
ure 36. At terminal A, the RDOG disables the PLTG/
FDOG trip/key function via OR-9A, AND-45A, AND-
30 and AND-45. At terminal B, it will receive no car-
rier signal for permissive trip. The reverse-block logic
also provides the conventional TBM feature to pre-
vent false operation on power reversal.
It should be noted that a “block-the-block” logic is
also included in the circuit as shown in Figure 36.
The block-the-block logic is to prevent the reverse-
block logic from overblocking, as a result of the fol-
lowing system condition.
For example, the breaker is unequal-pole closing on
a ØG fault, i.e. pole A, then B, C. Referring to Figure
37, if, due to breaker contact asymmetry, the first
breaker contact to close is the one on the faulted
phase, the zero sequence (or negative sequence)
polarizing voltage will initially have a polarity opposite
to its fault-derived polarity. The reverse-looking
ground unit could pick up for a short period, issue a
blocking order and maintain it for 50 ms. Conse-
quently, the correct tripping will be delayed. The
block-the-block logic would prevent this delaying. The
reverse-block logic also includes the reverse looking
Z3P/Z3G units as shown in Figure 36.
12.5 THE BLOCKING SYSTEM
The Blockin system is more secure by using the
faster
∆
I and
∆
V information for carrier start.
12.6 SECURITY LOGIC FOR REVERSE FAULT
WITH FAULT RESISTANCE.
There is an inordinately high influence of ct lead
resistance for a low voltage MPS test when using the
Motor-Generator set as one of the test sources. It
produces virtually a 90
°
phase shift in the polarizing
voltage with respect to the angle between sources,
causing undesired operation. Even though this is an
MPS-related phenomenon and would pose no prob-
lem for an actual power system, a forward phase
directional function FDOP is included in the design to
prevent this from occurring. (Refer to Figure 25,
AND-144C and AND-144D).
Section 12. UNIQUE FUNCTION OF MDAR (REL-300)
VERSION 2.60 SYSTEMS
