BC_27 are set to open by setting the appropriate module inputs as follows. In the
functional block diagram, 0 and 1 are designated 0=FALSE and 1=TRUE:
•
QB7_OP = 1
•
QB7_CL = 0
•
QC71_OP = 1
•
QC71_CL = 0
•
BB7_D_OP = 1
•
BC_17_OP = 1
•
BC_17_CL = 0
•
BC_27_OP = 1
•
BC_27_CL = 0
•
EXDU_BPB = 1
•
VP_BB7_D = 1
•
VP_BC_17 = 1
•
VP_BC_27 = 1
If there is no second busbar WA2 and therefore no QB2 disconnector, then the
interlocking for QB2 is not used. The state for QB2, QC21, BC_12, BC_27 are set
to open by setting the appropriate module inputs as follows. In the functional block
diagram, 0 and 1 are designated 0=FALSE and 1=TRUE:
•
QB2_OP = 1
•
QB2_CL = 0
•
QC21_OP = 1
•
QC21_CL = 0
•
BC_12_CL = 0
•
BC_27_OP = 1
•
BC_27_CL = 0
•
VP_BC_12 = 1
8.3.3
Interlocking for bus-coupler bay ABC_BC
IP14144-1 v2
1MRK 511 423-UEN A
Section 8
Control
Bay control REC650 2.2 IEC
133
Application manual
