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abaco systems SBC329 3U VPX, Hardware Reference Manual

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abaco systems SBC329 3U VPX Hardware Reference Manual Download Page 135

 

Publication No. SBC329-HRM/1 

  

Index  135 

R

 

Real-Time Clock ........................................................... 66 
Recovery Boot ............................................................... 21 
REFCLK ......................................................................... 53 
Registers ........................................................................ 80 

Ancillary/Audio Availability ................................. 96 
AXIS Clock Control................................................. 85 
AXIS Clock Frequency............................................ 85 
AXIS Timestamp ..................................................... 85 
Backplane Status ................................................... 102 
BIOS/SPI Control ..................................................... 83 
BIT Control & Status ............................................... 84 
Board ID ................................................................... 81 
Board ID String ........................................................ 83 
Board Jumper Link Status .................................... 104 
Board Revision ........................................................ 81 
Boot Location Status ............................................. 104 
COM Port 4-Wire Configuration .......................... 93 
COM Port Availability ........................................... 93 
COM Port Enable .................................................... 99 
COM Port Loopback Enable ................................ 100 
COM Port Mode ...................................................... 99 
COM Port Modem Configuration ......................... 93 
COM Port RS485 Auto Direction Control .......... 100 
Display Availability ................................................ 95 
Display-Port Display Availability ........................ 96 
DVI/HDMI Display Availability ........................... 96 
Ethernet Port Availability ...................................... 92 
FPGA Revision ........................................................ 81 
Front Panel Configuration ..................................... 97 
GPIO Active Low/High .......................................... 89 
GPIO Both Edges..................................................... 90 
GPIO Direction ........................................................ 89 
GPIO In ..................................................................... 89 
GPIO Interrupt Enable ........................................... 89 
GPIO Interrupt Status ............................................. 90 
GPIO Level/Edge..................................................... 89 
GPIO Out .................................................................. 89 
GPIO15 to GPIO8 Availability .............................. 90 
GPIO7 to GPIO0 Availability ................................ 90 
LED Control ............................................................. 83 
NVRAM Memory Space Page ............................... 84 
SATA Port Availability .......................................... 94 
Scratchpad .............................................................. 102 
SDD Cache Flush Control .................................... 101 

R (continued)

 

Registers (continued) 

SSD Availability ...................................................... 98 
SSD Erase Control ................................................. 101 
SSD Secure Hardware Erase Capability .............. 98 
SSD Status .............................................................. 103 
Test .......................................................................... 102 
Timer 0 Control & Status 1 .................................... 86 
Timer 0 Control & Status 2 .................................... 86 
Timer 0 Data Bytes 0 to 3 ....................................... 87 
Timer 0 IRQ Clear ................................................... 86 
Timer 1 Control & Status 1 .................................... 86 
Timer 1 Control & Status 2 .................................... 86 
Timer 1 Data Bytes 0 to 3 ....................................... 88 
Timer 1 IRQ Clear ................................................... 86 
UART Enable ........................................................... 98 
USB2.0 Port 15 to 8 Availability ............................ 95 
USB2.0 Port 7 to 0 Availability .............................. 94 
USB3.0 Port 15 to 8 Availability ............................ 95 
USB3.0 Port 7 to 0 Availability .............................. 95 
VGA Display Availability ...................................... 96 
VPX Control ........................................................... 101 
VPX GDISC1 Active High/Low ............................ 91 
VPX GDISC1 Availability ...................................... 92 
VPX GDISC1 Both Edges ....................................... 92 
VPX GDISC1 Direction........................................... 91 
VPX GDISC1 In ....................................................... 91 
VPX GDISC1 Interrupt Enable .............................. 91 
VPX GDISC1 Interrupt Status ............................... 92 
VPX GDISC1 Level/Edge ....................................... 91 
VPX GDISC1 Out .................................................... 91 
Watchdog Timer Control & Status LS Byte ......... 82 
Watchdog Timer Control & Status MS Byte........ 82 
Watchdog Timer Refresh ....................................... 82 
Write Protection Status ........................................ 103 
XMC I/O Configuration ......................................... 97 
XMC Status ............................................................ 102 

Related Documents ........................................................ 4 
Reliability .................................................................... 121 
Resets ............................................................................. 77 

Board Reset LED ..................................................... 75 
Maskable .................................................................. 53 
Sequence and Timing ............................................. 28 

Revision State ............................................................... 18 
RTMs ..................................................................... 27, 126 

 

 

Summary of Contents for SBC329 3U VPX

Page 1: ...Hardware Reference Manual SBC329 3U VPX Single Board Computer Edition 1 Publication No SBC329 HRM 1 ...

Page 2: ...ed Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of Directive 2012 19 EU of the European Parliament of 4 July 2012 on Waste Electrical and Electronic Equipment Abaco Systems Limited will evaluate requests to take back products purchased by our customers before August 13 2005 on a case...

Page 3: ... of the same document Numbers All numbers are expressed in decimal except addresses and memory or register data which are expressed in hexadecimal Where confusion may occur decimal numbers have a D subscript and binary numbers have a b subscript The prefix 0x shows a hexadecimal number following the C programming language convention Thus One dozen 12D 0x0C 1100b The multipliers k M and G have thei...

Page 4: ...s are saved under their original file names in the same directory on a server PC hard drive or similar If you are accessing this document via the Abaco website cross document links will not work If you are accessing this document in hard copy or downloaded form check the Abaco website to ensure that you have the latest version Third Party Documents Due to the complexity of some of the parts used o...

Page 5: ... http www vita com For VPX VITA 46 and XMC VITA 42 standards http www ieee com For IEEE standards http www pcisig org For PCI Bus standards http www intel com For processor chip set and Ethernet controller information http www plxtech com For PCIe switch device information http www latticesemi com For FPGA and PSU Monitor device information http www national com For LM92 temperature sensor device ...

Page 6: ...e Technical Support database and allocate it a unique Case number for use in any future correspondence Alternatively you may also contact Abaco s Technical Support via LINK support abaco com Returns If you need to return a product there is a Return Materials Authorization RMA tool available via the web site Embedded Support page LINK https www abaco com embedded support Do not return products with...

Page 7: ...ne Installation 23 4 Installation and Power Up Reset 25 4 1 Power Supply Requirements 25 4 2 Board Keying 26 4 3 Board Installation Notes 26 4 4 Connecting to SBC329 27 4 5 Reset and Power up Sequence 28 4 6 BIOS Setup Utility 28 4 7 First Boot Menu 29 4 8 About the Setup Menus 30 4 9 Main Menu 31 4 10 Advanced Menu 32 4 11 Chipset Menu 33 4 12 Abaco Menu 34 4 12 1 Board Build Information 35 4 12 ...

Page 8: ...Fabric Gigabit Ethernet 55 5 7 1 BASE T BASE BX Variant SBC329 xxx1xxxxx 56 5 7 2 Dual BASE T Variant SBC329 xxx2xxxxx 57 5 8 GPIO 57 5 9 PCIe Switch 58 5 9 1 Switch Configuration EEPROM 58 5 10 USB 59 5 11 Serial Ports 60 5 11 1 RS422 RS485 Mode 61 5 12 SATA 61 5 13 Video 62 5 14 LPC Bus 63 5 14 1 FPGA 63 5 14 2 Trusted Platform Monitor 63 5 15 Mezzanine Site 64 5 15 1 XMC Connectors 64 5 15 2 I ...

Page 9: ...Control Register 0x622 83 6 7 BIOS SPI Control Register 0x625 83 6 8 BIT Control and Status Register 0x629 84 6 9 NVRAM Memory Space Page Register 0x635 84 6 10 AXIS Registers 85 6 11 Timer Registers 86 6 11 1 Timer 0 Control and Status Register 1 0x650 Timer 1 Control and Status Register 1 0x658 86 6 11 2 Timer 0 Control and Status Register 2 0x651 Timer 1 Control and Status Register 2 0x659 86 6...

Page 10: ...4 USB3 0 Port 15 to 8 Availability Register 0x6A8 95 6 25 Display Availability Register 0x6A9 95 6 26 VGA Display Availability Register 0x6AA 96 6 27 DVI HDMI Display Availability Register 0x6AB 96 6 28 Display Port Display Availability Register 0x6AC 96 6 29 Ancillary Audio Availability Register 0x6AD 96 6 30 Front Panel Configuration Register 0x6AE 97 6 31 XMC I O Configuration Register 0x6AF 97...

Page 11: ...quirements 117 A 2 2 Power Consumption 118 A 2 3 Current Consumption SBC329 xxxxxx1xx Variant 118 A 2 4 Current Consumption SBC329 xxxxxx2xx Variant 120 A 2 5 XMC Site Current Provision 120 A 2 6 Power Supply Sequencing 120 A 3 Mechanical Specification 121 A 4 Reliability MTBF 121 A 5 Environmental Specifications 122 A 6 Product Codes 124 A 7 Software Support 125 A 8 I O Modules 126 A 9 Test Acces...

Page 12: ...bility 61 Table 5 12 Video Port Summary 62 Table 5 13 DVI Signal Mapping 62 Table 5 14 XMC I O Routing Availability 64 Table 5 15 Mezzanine Site Signal Mapping 65 Table 5 16 I2 C Bus Addresses 66 Table 5 17 DIP Switch Options 67 Table 5 18 BMM I2 C Bus Devices 70 Table 5 19 Temperature Sensor Monitor Locations 70 Table 5 20 PMBus Device Data Monitored 71 Table 5 21 LED Summary 73 Table 5 22 BIT LE...

Page 13: ...Consumption 5V Rail Vs3 119 Table A 8 Current Consumption P3V3_AUX 119 Table A 9 Current Consumption VBAT 119 Table A 10 Power Measurement Conditions 119 Table A 11 Current Consumption SBC329 xxxxxx2xx Variant 5V VS3 Rail 120 Table A 12 XMC Site Current Provision 120 Table A 13 Mechanical Construction 121 Table A 14 Reliability MTBF 121 Table A 15 Convection cooled Environmental Specifications 122...

Page 14: ... 4 10 Hardware Protection Sub menu 40 Figure 4 11 CPU Speed Locking Configuration Sub menu 41 Figure 4 12 Network Boot Configuration Sub menu 42 Figure 4 13 Security Menu 43 Figure 4 14 Boot Menu 44 Figure 4 15 Save Exit Menu 45 Figure 5 1 Block Diagram 46 Figure 5 2 SLT3 PAY 2F2T 14 2 5 Port Layouts 52 Figure 5 3 SLT3 PAY 2F2U 14 2 3 Port Layouts 52 Figure 5 4 Gigabit Ethernet Channel Configurati...

Page 15: ... provides a DDR4 SDRAM interface with ECC For more exacting SWaP requirements the SBC329 is also available with the E3 1505L v6 lower power processor The Intel CM238 PCH provides three SATA interfaces three USB ports an LPC interface and a Serial Peripheral Interface supporting SPI boot Flash The XMC site connects 24S X8d X12d I O signals to the VPX backplane and has a x8 PCIe interface supporting...

Page 16: ...d before installing any device To minimize electric shock hazard connect the equipment chassis and rack enclosure to an electrical ground If AC power is supplied to the rack enclosure the power jack and mating plug of the power cable must meet IEC safety standards 1 1 1 Flammability The SBC329 circuit board is made by a UL recognized manufacturer and has a flammability rating of UL94V 1 1 1 2 EMI ...

Page 17: ...e the SBC329 by the edges or front panel Figure 1 2 ESD Label Present on Board Packaging 1 1 5 Heatsink CAUTIONS Do not remove the heatsink There are no user alterable components underneath the heatsink so users should have no reason to remove it Users should not attempt reattachment of the heatsink as this requires precise torque on the screws attaching the heatsink to the PCB Over tightening the...

Page 18: ...y 2 1 Box Contents Checklist 1 SBC329 in antistatic packaging 2 Embedded Software License Agreement ABACO SLA 001 01 2 2 Identifying Your Board The SBC329 is identified by labels at strategic positions These can be cross checked against the Advice Note provided with your delivery Identification labels like the example shown in Figure 2 1 attached to the shipping box and the antistatic bag give ide...

Page 19: ...s of the board build levels 4 and 5 there is also a label like the example shown in Figure 2 3 attached to the front panel Figure 2 3 Product Label Conduction cooled Product See the Product Codes section in Appendix A for more details on the product code SBC329 xxxxxxxxx ...

Page 20: ...n the pin posts and then cover these wire wrapped links with the same conformal coating as that used on the board usually ACRYLIC 1B73AP contact Technical Support for details if needed This will provide a reliable connection under heavy shock and vibration conditions and further prevent oxidation of the connection due to moisture ingress Figure 3 1 Link Positions The diagram above shows standard 2...

Page 21: ...on will enable board operation to be proven before tackling any further configuration issues 3 3 1 Recovery Boot Link P3 This link allows user selection of the SPI Flash device from which the SBC329 boots as follows Table 3 1 P3 Link Setting Setting Meaning In SBC329 boots from Recovery device Out SBC329 boots from Main device default In normal operation a jumper is not fitted on this link and the...

Page 22: ...locked default NOTES This link controls the hardware write protection of the configuration EEPROM devices Some devices also require software write protection which must be provided by the operating system or the BIOS see the BIOS Setup Utility in section 4 The VPX backplane Non Volatile Memory Read Only NVMRO signal on connector P0 pin A4 must also be set inactive low before any configuration EEPR...

Page 23: ... 8 0 mm Figure 3 2 Keepout Area 3 4 1 XMC Installation XMCs supplied by Abaco are delivered with a full kit of parts for mounting them Fitting is described in the XMC Installation application note An XMC ordered with an SBC329 can be supplied fitted by Abaco if required LINK XMC Installation Application Note publication number HN4 5 16 It will usually be necessary to install driver software or imp...

Page 24: ...ude of the effect of the XMC largely depends on the XMC thermal solution and needs to be considered on a case by case basis Contact Abaco for more details 3 4 2 XMC Connectors The SBC329 is fitted with standard VITA 42 XMC compatible connectors However there is an option to upgrade to VITA 61 connectors which offer a superior bandwidth and increased reliability See the Product Codes section for mo...

Page 25: ...x variant Up to 14 9 A 5V 5 2 5 P3V3_AUX Up to 0 4 A 3 3V 5 NOTE The above table shows requirements for the SBC329 without an XMC fitted XMCs can draw power from both VS2 and VS3 so this should be factored in when determining system level specifications P12V_AUX and N12V_AUX are not required for board operation but are routed to the auxiliary supplies of the XMC site The VBAT supply may be used to...

Page 26: ...tor ejector handle to ensure that the backplane connectors mate properly with the backplane The captive screws at the top and bottom of the front panel allow the board to be tightly secured in position which provides continuity with the chassis ground of the system 3 Conduction cooled versions of the SBC329 have screw driven wedgelocks to provide the necessary mechanical thermal interface Correct ...

Page 27: ...fore connecting anything to the RTM The following items are required The appropriate RTM VPX3UX301 or VPX3UX601 An SIOX600 breakout panel and a null modem 9 way D to 9 way D type cable for connecting COM1 to a control terminal or PC running terminal emulation software For each Ethernet port a CAT5 or better straight through patch cable for 10 100 1000BASE T CAUTION Ensure that the board variant su...

Page 28: ...ers a sleep state and remains there until the SYSRESET signal is de asserted It is normal to see the Power Good LED DS407 turn off when the SYSRESET signal is asserted Assuming the backplane SYSRESET signal is not active at the end of the reset power up sequence the SBC329 may depending on whether BIT is available and its configuration enter the BIOS Setup utility This is described below 4 6 BIOS ...

Page 29: ...ue with the boot The First Boot menu is accessed by pressing the F7 key at the very beginning of the boot cycle The selection made from this screen applies to the current boot only and will not be used during the next boot up of the SBC329 If you have trouble accessing the First Boot menu from the Boot menu disable Fast Boot Exit saving changes and retry accessing this feature Figure 4 1 First Boo...

Page 30: ...sub menu and then press Enter to pick that sub menu or option for altering To step through the range of available settings e g enabled disabled for that option use the and keys When in a sub menu the Setup menu selection line shows the top level menu selection only This section shows examples from a working SBC329 While the general type and level of information displayed should be similar for your...

Page 31: ...ntry to Setup It reports details on the BIOS firmware the board and the processor It also allows the user to set the System Language English is the default and currently the only option and the SBC329 clock calendar although without battery back up any power cycle will reset the clock Figure 4 2 Main Menu ...

Page 32: ...set settings CAUTION Changes made from some menus can cause the SBC329 to malfunction If problems are detected after changes have been made reboot the board and access the Setup Select the Save Exit menu pick Restore Defaults then save these changes and reboot the board e g by picking Save Changes and Reset Figure 4 3 Advanced Menu ...

Page 33: ... for the chipsets are processor dependent take care when changing settings from the defaults set by Abaco CAUTION Changes made from some menus can cause the SBC329 to malfunction If problems are detected after changes have been made reboot the board and access the Setup Select the Save Exit menu pick Restore Defaults then save these changes and reboot the board e g by picking Save Changes and Rese...

Page 34: ...ard Computer Publication No SBC329 HRM 1 4 12 Abaco Menu This allows selection of the various options that are specific to the SBC329 for example the CPU speed locking configuration and DIP Switch settings Figure 4 5 Abaco Menu ...

Page 35: ...wer Up Reset 35 4 12 1 Board Build Information When this item is selected the SBC329 reports its specific build configuration i e I O options that depend on the variant ordered see section A 6 to the user Figure 4 6 Board Build Information Sub menu ...

Page 36: ...protection of the on board SSD NVRAM and configuration EEPROMs It can also be used to enable the Backplane REFCLK output See section 5 17 1 for more information To activate a new configuration select the required settings and then select the PROGRAM DIP SWITCH option NOTE Ensure that the DIP switch is write enabled before selecting the PROGRAM DIP SWITCH option by ensuring that the backplane NVMRO...

Page 37: ... FPGA Setup Status This allows some on board functions that are controlled by the FPGA to be configured and or their status reported To access these options pick FPGA from the Abaco menu to display a sub menu like the one shown below Figure 4 8 FPGA Setup Status Sub menu ...

Page 38: ...e user to set some aspects of the on board PCIe switch configuration Settings are selected via this menu and then activated by programming them into the configuration EEPROM They are then loaded into the switch configuration registers the next time the board is reset or power cycled Figure 4 9 PLX Switch Sub menu ...

Page 39: ...g used in a development backplane to connect the Expansion Plane forcing Gen1 mode using this method is recommended NOTE Gen3 operation is not guaranteed and its operation should be validated by the end user before use Program EEPROM Once the required PCIe switch settings have been made select this option to program the configuration into the EEPROM The new configuration is only activated after th...

Page 40: ...40 SBC329 3U VPX Single Board Computer Publication No SBC329 HRM 1 4 12 5 Hardware Protection This allows the user to view or alter hardware protection Figure 4 10 Hardware Protection Sub menu ...

Page 41: ...eep the junction temperature below the maximum level In many applications throttling is not desirable since it can lead to non deterministic operation The SBC329 therefore has a feature that allows the user to lock the operating frequency of the processor at a known value to mitigate the effects of thermal throttling Appendix B provides information on the thermal characteristics of the SBC329 whic...

Page 42: ...s is disabled by default To enable booting from the network pick Network Boot from the Abaco menu to display a sub menu like the one shown below This allows enabling of PXE boot on each network port Figure 4 12 Network Boot Configuration Sub menu Press F4 to save and exit the BIOS Setup menus NOTE To boot from the network some operating systems require that the network driver be set to boot in the...

Page 43: ...se passwords If both passwords are to be used the Administrator password must be set first Figure 4 13 Security Menu CAUTION Take care when setting passwords Once a password is set there is no method available to the user to reset it without using that original password If a password is lost the BIOS will need to be reprogrammed Should this event occur contact Technical Support for assistance ...

Page 44: ...ting from a remote network The devices shown in this menu are the bootable devices detected during POST If an installed drive does not appear verify the hardware installation Also available in this menu are Boot Configuration settings that allow the user to set how the SBC329 acts for example whether to use Fast Boot Figure 4 14 Boot Menu ...

Page 45: ...s on saving Setup selections and exiting Setup Figure 4 15 Save Exit Menu If changes have previously been made from the Setup menus and the SBC329 malfunctions reboot the board and select this screen Pick Restore Defaults then save these changes and reboot the board e g by picking Save Changes and Reset ...

Page 46: ...ly through mechanisms provided by the Operating System s Board Support Package and not directly by application software If a standard operating system is not being used then it is recommended that applications are written in such a way as to minimize direct access to hardware resources bearing in mind that changes may be necessary to support future iterations of the hardware Abaco supported Operat...

Page 47: ...VPX backplane two USB2 0 and one USB3 0 Up to three 6 Gb s SATA channels connected to the VPX backplane 8 lanes of PCIe configurable as one x8 or two x4 links to the backplane with non transparent operation Up to four bits of General Purpose I O with interrupt capability One x8 PCIe Gen3 capable XMC site Elapsed time indicator Watchdog timer Ambient and chip temperature sensors System Management v...

Page 48: ...Ie Gen3 interface 64 bit memory controller with ECC Integrated Intel HD Graphics P630 GT2 The following table shows the Processor Stock Keep Units SKUs supported Contact Abaco for the latest processor options and speeds Table 5 1 Supported Processor SKUs SKU Core Frequency GHz Number of Cores Cache Size MB Specified TDP Watts E3 1505M v6 3 0 4 8 45 E3 1505L v6 2 2 4 8 25 NOTE The CPU operating fre...

Page 49: ...030 01 L D A connector in accordance with Intel recommendations and conforms to the Intel eXtended Debug Port XDP standard pin out allowing probes from various vendors to be used A TAC is available if required part number SBC328TST 11 Contact Abaco for ordering information 5 3 Memory 5 3 1 SDRAM The SBC329 provides two ranks of DDR4 SDRAM with ECC The following table shows the RAM configuration Ta...

Page 50: ...ust storage area An LED DS408 shows device activity see the LEDs section LINK For more details on the SSD see http www siliconmotion com Overall drive capacity is dictated by available technology Currently the SBC329 can support up to 32 GB of NAND Flash although higher densities are expected to be available in the future See the Product Codes section for available device types or contact Abaco fo...

Page 51: ...resses of the pages within the devices are set by the NVRAM page register TIP Only access this device using proprietary driver software The NVRAM device has very high read write endurance 1014 cycles and stated data retention is greater than 10 years LINK For more details on the FRAM see http www Cypress com Write Protection Each area of the NVRAM can be independently write protected by setting bi...

Page 52: ...his slot profile Figure 5 2 SLT3 PAY 2F2T 14 2 5 Port Layouts In the two 1000BASE BX ports configuration the SBC329 will fit in this slot profile Figure 5 3 SLT3 PAY 2F2U 14 2 3 Port Layouts Slot profiles define the physical layout of the fabric ports whereas module profiles include information about the fabric protocol A backplane will define a slot profile for each slot but that slot is compatib...

Page 53: ...h configuration EEPROM to be set up accordingly 5 4 3 Module Maskable Reset OpenVPX supports a second reset input from the backplane P1 pin G15 which may be masked under software control The SBC329 is hard reset when the Maskable Reset backplane signal is asserted for more than 10 µS unless masked by software in the FPGA The reset is not masked by default The SBC329 is also able to drive the Maska...

Page 54: ...wo x8 Links Mode Signal PCIe P1 Pin Link Assignment Two x8 Links Mode PCIE_DP01_RX0P A1 Link A PCIE_DP02_RX0P A5 Link B PCIE_DP01_RX0N B1 PCIE_DP02_RX0N B5 PCIE_DP01_TX0P D1 PCIE_DP02_TX0P D5 PCIE_DP01_TX0N E1 PCIE_DP02_TX0N E5 PCIE_DP01_RX1P B2 PCIE_DP02_RX1P B6 PCIE_DP01_RX1N C2 PCIE_DP02_RX1N C6 PCIE_DP01_TX1P E2 PCIE_DP02_TX1P E6 PCIE_DP01_TX1N F2 PCIE_DP02_TX1N F6 PCIE_DP01_RX2P A3 PCIE_DP02_...

Page 55: ...ation 5 6 1 PCIe Gen3 Operation The SBC329 is compatible with PCIe Gen3 operation across the backplane The ability to operate at Gen3 depends on the physical parameters of the complete channel i e the backplane the SBC329 and the link partner so Gen3 operation should be verified on a system by system basis Abaco has verified Gen3 operation using an SBC329 at each end of the link in a test chassis ...

Page 56: ...are connected to the VPX P1 connector as follows Table 5 4 ETH0 ETH1 ETH2 Pin Mapping BASE T BASE BX Variant Signal P1 Pin Signal P1 Pin Signal P1 Pin ETH0_0P A13 ETH1_RXP B16 ETH2_RXP A15 ETH0_0N B13 ETH1_RXN C16 ETH2_RXN B15 ETH0_1P D13 ETH1_TXP E16 ETH2_TXP D15 ETH0_1N E13 ETH1_TXN F16 ETH2_TXN E15 ETH0_2P B14 ETH0_2N C14 ETH0_3P E14 ETH0_3N F14 CAUTION When in this configuration BASE BX signal...

Page 57: ...ends on the build variant The table below summarizes the availability and signal routing Table 5 6 GPIO Line Signal Availability GPIO Line Build Variant Availability Pin Alternate Function 0 SBC329 xxxx3xxxx P2 G3 COM2_TXD TXD_A 1 SBC329 xxxx3xxxx P2 G5 COM2_RXD RXD_A 2 SBC329 xxxx1xxxx SBC329 xxxx3xxxx P2 G7 COM2_RTS TXD_B AXIS_CLK 3 SBC329 xxxx1xxxx SBC329 xxxx3xxxx P2 G9 COM2_CTS RXD_B AXIS_RST...

Page 58: ...or boards in a multi peer PCIe system 5 9 1 Switch Configuration EEPROM A serial EEPROM is connected to the switch to allow the initial configuration to be programmed by software Write protection of this EEPROM is controlled by a BIOS setup option which is interlocked with the Configuration EEPROM Write Enable Link P6 and the backplane NVMRO signal i e a jumper must be fitted on the link and NVMRO...

Page 59: ... include re drivers on USB_P2 signals Two power switches are used to switch VBUS power to the ports USB_P0 and USB_P1 share a single backplane pin for VBUS power maximum 1A for both ports USB_P2 has its own VBUS power pin maximum 1A for this port The power switches provide over current protection OCP and can signal over current conditions to the PCH NOTE The PCH does not support OCP for each port ...

Page 60: ...Table 5 9 COM Port Connections Port Build Variant Availability RS232 Signal Set RS422 RS485 Signal Set COM1 All variants 2 wire TXD RXD Not available COM2 SBC329 xxxx1xxxx 2 wire TXD RXD Not available SBC329 xxxx2xxxx 4 wire TXD RXD RTS CTS 4 wire TXD_A TXD_B RXD_A RXD_B SBC329 xxxx3xxxx Not available Not available COM3 Permanent connection to BMM The following table shows the COM1 and COM2 routin...

Page 61: ...eripherals such as hard disk drives or CD DVD drives and the remaining port is connected directly to the on board SSD device All backplane ports can operate at SATA Revision 3 0 data transfer rates up to 6 Gb second The operating mode of the controller can be set in the BIOS setup menus by selecting the SATA configuration menu in the Advanced tab see section 4 10 The default setting is SATA 3 Gb s...

Page 62: ...C_CLK E12 C8 TX1_P A11 D9 DDC_DATA F12 E8 TX2_N E11 C10 HPD G13 F8 TX2_P D11 B10 Connection to the video ports is via a Mini HDMI Type C connector or a DVI I connector depending on the RTM type and port Conversion cables and adaptors may be required to connect the port to the desired display type DVI or HDMI The Graphics Controller GT2 is integrated into the Xeon E3 1505M v6 processor and it inclu...

Page 63: ...rious functions See section 5 22 for more details 5 14 2 Trusted Platform Monitor The SBC329 includes a Trusted Platform Monitor TPM device for security key generation and storage The device includes an internal EEPROM for key storage The device is compliant with Trusted Computing Group TCG PC Client Specific TPM Interface Specification version 1 2 and can generate 2048 bit RSA keys in 500 ms ...

Page 64: ...here is an option to upgrade to VITA 61 connectors which offer a superior bandwidth and increased reliability See the Product Codes section 5 15 2 I O Routing Rear I O tracking is provided from the J16 connector to the rear VPX connectors in accordance with VITA 46 9 Depending on build variant the following configurations are available Table 5 14 XMC I O Routing Availability Build Variant I O Avai...

Page 65: ...1 B2 J16_IO_E03 B8 J16_IO_E07 B12 J16_IO_C12 E3 J16_IO_A11 E9 J16_IO_A09 E13 J16_IO_C13 D3 J16_IO_B11 D9 J16_IO_B09 D13 J16_IO_F12 B3 J16_IO_D11 B9 J16_IO_D09 B13 J16_IO_F13 A3 J16_IO_E11 A9 J16_IO_E09 A13 J16_IO_C14 F4 J16_IO_A13 F10 J16_IO_A15 F14 J16_IO_C15 E4 J16_IO_B13 E10 J16_IO_B15 E14 J16_IO_F14 C4 J16_IO_D13 C10 J16_IO_D15 C14 J16_IO_F15 B4 J16_IO_E13 B10 J16_IO_E15 B14 J16_IO_C16 E5 J16_...

Page 66: ...nd report the RTC function The leap year determination for adding a 29th day to February does not take into account the end of the century exceptions 5 17 I2 C Bus The PCH has a single I2C bus supporting SMBus 2 0 I2C devices on the board are connected to this bus as shown below Figure 5 6 I2 C Bus Structure The table below summarizes the I2C slave addresses of the devices in the system Where I2C ...

Page 67: ...OTE Setting this bit to a 0 may cause instability if an operating system is installed on the SSD REG0 bit 5 NON_MUXED_OUT Backplane PCIe REFCLK enable 0 REFCLK is not driven default 1 REFCLK is driven at 100 MHz REG1 bit 0 Not connected Run BIT reserved for use by FSP 0 Boot into the FSP menu 1 Run BIT REG1 bit 1 Not connected BIT Verbose mode reserved for use by FSP 0 BIT Verbose mode disabled 1 ...

Page 68: ...plane NVMRO signal on P0 pin A4 is inactive NOTES The write protection status can only be changed when a TAC is fitted to the SBC329 The integrated temperature sensor in this device is not used by software and is not available for customer use However it will respond to relevant addresses on the SMBus 5 17 3 Elapsed Time Indicator A Dallas DS1682 ETI logs the amount of time for which the SBC329 ha...

Page 69: ...System Management bus on the P0 connector via isolation buffers On board I2C bus for access to sensor devices XMC System Management bus VPX geographic address Internal FRU Field Replaceable Unit ROM containing the board part number and serial number The BMM can reset or power off the SBC329 in response to a System Management request The BMM can control the state of the BIT Fail LED DS404 to indica...

Page 70: ...TC3880 power supply PMBus interface P0V9 P0V9A internal rails 0x40 0x80 LT2975 Backplane PMBus power monitor 0x5C 0xD8 5 18 1 Board Temperature Sensor A Texas Instruments TPM442A digital temperature sensor monitors the locations shown below which can be used by system health monitoring software either on the SBC329 or on an external IPMI controller to determine the ambient operating temperature of...

Page 71: ... Input Voltage current output voltage current inductor temperature P0V9A 0 9V LTC3880 1 page 1 Input Voltage current output voltage current inductor temperature VDDQ 1 2V LTC3880 2 page 0 Input Voltage current output voltage current inductor temperature VCC_IO 0 95V LTC3880 2 page 1 Input Voltage current output voltage current inductor temperature P1V0 1 0V LTC3880 3 page 0 Input Voltage current o...

Page 72: ...as a start value The timers can be programmed to roll over on expiry and reload the initial start value or they can be programmed into one shot mode where they will stop counting when expired Together these features provide a highly flexible timer solution The FPGA timers are intended only to be used by Abaco software drivers See the relevant software manual for details 5 19 2 Watchdog Timers The ...

Page 73: ...2 5 GT s speed DS410 Backplane PCIe DP02 link status Green Steady on DP02 is linked at Gen3 8 GT s speed Flashing 2 Hz DP01 is linked at Gen2 5 GT s speed Flashing 1 Hz DP01 is linked at Gen1 2 5 GT s speed DS411 XMC PCIe link status Green Steady on XMC is linked at Gen3 8 GT s speed Flashing 2 Hz XMC is linked at Gen2 5 GT s speed Flashing 1 Hz XMC is linked at Gen1 2 5 GT s speed DS412 CPU PCIe ...

Page 74: ...BC329 has four software controlled LEDs to reflect the status of BIT or other boot software When used by BIT the LEDs have the following meanings Table 5 22 BIT LED Meanings LEDs Color Meaning When Lit DS437 Green BIT Pass DS404 Red BIT Fail DS402 Yellow BIT status 2 see BIT documentation DS403 Yellow BIT status 1 see BIT documentation LINK BIT for SBC329 Software Reference Manual publication numb...

Page 75: ... status of the CPU solder ball daisy chain When the chain is broken the LED will flash at approximately 2 Hz indicating that the CPU may not be soldered to the board properly If this occurs contact Technical Support for more information 5 20 3 SSD Activity LED DS408 This yellow LED is lit when there is SSD activity i e when the drive is being read from or written to 5 20 4 PCIe Link Status LEDs DS...

Page 76: ...ning When Off Meaning When Flashing DS432 ETH0 BASE T Link is present No link Activity DS422 Speed 1000 Mbps Speed 10 100 Mbps or no link DS436 ETH2 BASE T or BASE BX Link is present No link Activity DS435 Speed 1000 Mbps Speed 10 100 Mbps or no link DS434 ETH1 BASE BX Link is present No link Activity DS433 Speed 1000 Mbps No link 5 20 7 SATA Activity LED DS429 This green LED when lit shows that t...

Page 77: ...hich cannot be used to hold the board in reset and they may not result in a reset if the processor has crashed The table below summarizes the reset sources Table 5 26 Reset Sources Reset Source Reset Type Comments BIT Reset Request FPGA register Edge BIT LEDs and BIT status registers are not reset TAC reset switch Edge Cannot be used to hold the board in reset XMC reset Edge VPX SYSRESET must be a...

Page 78: ...ort AXIS Advanced Multiprocessor Integrated Software is a set of software modules that can be used to accelerate the design development testing and deployment of complex DSP and multiprocessing platforms for real time applications such as radar sonar communications and image processing AXIS requires two external hardware signals AXIS_CLK and AXIS_RST to allow boards to synchronize over the backpla...

Page 79: ...comply with this standard If you are fitting a XMC with a bezel yourself before fitting the module remove the blanking plate from the slot The XMC s bezel should fill the slot and may provide front panel connection to the module Abaco XMCs are delivered with a full kit of parts for mounting 5 23 2 Conduction cooled Versions Build Levels 4 and 5 In build levels 4 and 5 the SBC329 supports the VITA4...

Page 80: ...ilability Read only 0x650 Timer 0 C S1 Read Write 0x6A1 COM Port Availability Read only 0x651 Timer 0 C S2 Read Write 0x6A2 COM Port 4 Wire Configuration Read only 0x652 Timer 0 IRQ Clear Read Write 0x6A3 COM Port Modem Configuration Read only 0x654 Timer 0 Data Byte 0 LS Byte Read Write 0x6A4 SATA Port Availability Read only 0x655 Timer 0 Data Byte 1 Read Write 0x6A5 USB2 0 Port 7 to 0 Availabili...

Page 81: ...ly 0x6C7 Test Read only Any LPC I O ports not shown in the table above are reserved C S Control and Status CAUTION These registers are intended to be accessed only by proprietary driver software Other access to these registers could cause the SBC329 to malfunction NOTE The descriptions shown below are for reference only and are subject to change 6 1 Board ID Register 0x600 This returns the value 0...

Page 82: ...g a board reset Any read access returns 0x00 6 4 2 Watchdog Timer Control and Status Register LS Byte 0x60E Bits Read Write Description Default 7 to 1 Read only Reserved 0000000b 0 Read Write WDT enable 1 WDT enabled 0 WDT disabled 0b 6 4 3 Watchdog Timer Control and Status Register MS Byte 0x60F Bits Read Write Description Default 7 to 3 Read only Reserved 00000b 2 to 0 Read Write WDT timeout sel...

Page 83: ...it 0 sticky on BIT reset 6 Read onlya BIT Fail LED DS401 0 5 Read Write BIT Status 1 LED DS402 1 LED lit 0 LED not lit 0 sticky on BIT reset 4 Read Write BIT Status 2 LED DS403 1 LED lit 0 LED not lit 0 sticky on BIT reset 3 to 0 Read only Reserved 0000b a It is not possible to control the BIT Fail LED directly control is only possible via the BMM 6 7 BIOS SPI Control Register 0x625 Bits Read Writ...

Page 84: ...3 Read Write Fast BIT 1 Fast BIT enabled via BIOS setting 0 Fast BIT disabled 0 2 Read Write Fast Start 1 Fast Start enabled via BIOS setting 0 Fast Start disabled 0 1 Read only Reserved 0 0 Read Write BIT run 1 BIT has been run 0 BIT not been run 0 sticky when reset using HRESET request 6 9 NVRAM Memory Space Page Register 0x635 Bits 2 to 0 of this register make up bits 18 to 16 of the NVRAM addr...

Page 85: ...byte N A 6 10 2 AXIS Clock Frequency Register 0x64E This returns the AXIS master clock period in nanoseconds It returns the value 0xFA which equals 250 ns giving a 4 0 MHz clock 6 10 3 AXIS Clock Control Register 0x64F Bits Read Write Description Default 7 Read Write AXIS master enable 1 Drive AXIS clock onto GPIO2 and allow GPIO3 to be driven as AXIS reset GPIO2 and GPIO3 interrupts are automatic...

Page 86: ...ite Enable Timer IRQ 1 IRQ enabled 0 IRQ masked 0 6 11 2 Timer 0 Control and Status Register 2 0x651 and Timer 1 Control and Status Register 2 0x659 Bits Read Write Description Default 7 to 5 Read only Reserved 000b 4 Read Write Timer read latch select 1 Latch all timers on read of timer 0 LSBa 0 Latch individual timers on read of individual timer LSB 0 3 and 2 Read only Reserved 00b 1 Read Write ...

Page 87: ...nt timer default 0x00 Timer load default 0xFF 8 to 15 0x656 Timer 0 Data Byte 2 Current timer default 0x00 Timer load default 0xFF 16 to 23 0x657 Timer 0 Data Byte 3 most significant byte Current timer default 0x00 Timer load default 0xFF 24 to 31 Reading byte 0 latches the upper bits of the timer value to prevent rollover Writes Writes always update the timer load value irrespective of the settin...

Page 88: ...te 1 Current timer default 0x00 Timer load default 0xFF 8 to 15 0x65E Timer 1 Data Byte 2 Current timer default 0x00 Timer load default 0xFF 16 to 23 0x65F Timer 1 Data Byte 3 most significant byte Current timer default 0x00 Timer load default 0xFF 24 to 31 Reading byte 0 latches the upper bits of the timer value to prevent rollover Writes Writes always update the timer load value irrespective of ...

Page 89: ...gister 0x672 Bits 3 to 0 show the direction input or output of GPIO3 to GPIO0 respectively as follows 1 Output 0 Input default 6 14 4 GPIO Interrupt Enable Register 0x673 Bits 3 to 0 enable interrupts for GPIO3 to GPIO0 respectively as follows 1 Interrupt enabled 0 Interrupt masked default 6 14 5 GPIO Level Edge Register 0x674 Bits 3 to 0 set the interrupt detection sensitivity of interrupt pins G...

Page 90: ...14 9 GPIO7 to GPIO0 Availability Register 0x678 This allows software easily to determine which signals of GPIO7 to GPIO0 are available All GPIO signals used shared backplane pins and are only available when the board is configured with the appropriate build option Bits Description Default 7 to 4 GPIO7 to GPIO4 are not available 0x0 3 GPIO3 availability shared with COM2_CTS RXD_B signal 1 GPIO3 ava...

Page 91: ...PX GDISC1 Direction Register 0x68A Bit 7 shows the direction output or input of the GDISC1 pin as follows 1 Output 0 Input default 6 15 4 VPX GDISC1 Interrupt Enable Register 0x68B Bit 7 enables interrupts for the GDISC1 pin as follows 1 Interrupt enabled 0 Interrupt masked default 6 15 5 VPX GDISC1 Level Edge Register 0x68C Bit 7 sets the interrupt detection sensitivity of the GDISC1 pin level or...

Page 92: ...lability Register 0x690 Bit 7 shows the availability of the GDISC1 pin as follows 1 GDISC1 is available 0 GDISC1 is not available default 6 16 Ethernet Port Availability Register 0x6A0 Availability of Ethernet ports 0 to 2 is build option dependent NOTE Even when a port is not available due to a build option it may still be visible to software Bits Description Default 7 to 3 Ethernet ports 7 to 3 ...

Page 93: ...figuration of COM2 is build option dependent Bits Description Default 7 to 2 Reserved 000000b 1 COM2 4 wire configuration 0 COM2 is available in 2 wire TX RX mode only 1 COM2 is available in 4 wire RS232 or RS422 mode N A 0 COM1 4 wire configuration COM1 is only ever available in 2 wire mode 0 COM1 is available in 2 wire TX RX mode only 0 6 19 COM Port Modem Configuration Register 0x6A3 Bits Descr...

Page 94: ...vailable 00000b 2 SATA port 2 availability 0 SATA port 2 is not available 1 SATA port 2 is available N A 1 SATA port 1 availability 0 SATA port 1 is not available 1 SATA port 1 is available N A 0 SATA port 0 availability SATA port 0 is always available 1 SATA port is available 1 6 21 USB2 0 Port 7 to 0 Availability Register 0x6A5 Bits Description Default 7 to 2 USB2 0 ports 7 to 2 availability USB...

Page 95: ...ble 0 USB3 0 port is not available 00b 6 23 USB2 0 Port 15 to 8 Availability Register 0x6A7 As USB2 0 ports 15 to 8 are not available this register returns 0x00 6 24 USB3 0 Port 15 to 8 Availability Register 0x6A8 As USB3 0 ports 15 to 8 are not available this register returns 0x00 6 25 Display Availability Register 0x6A9 Availability of display 1 is build option dependent Bits Description Default...

Page 96: ...play type is not DVI HDMI 000000b 1 Display 1 DVI HDMI availability 0 Display type is not DVI HDMI 1 Display type is DVI HDMI N A 0 Display 0 DVI HDMI availability Display 0 is always DVI HDMI 1 Display type is DVI HDMI 1 6 28 Display Port Display Availability Register 0x6AC As no Display Port displays are available this returns 0x00 6 29 Ancillary Audio Availability Register 0x6AD Bits Descriptio...

Page 97: ...x6AF X8d and X24S are build option dependent Bits Description Default 7 P64s compliant configuration PMC is not available 0 I O is not P64 compliant 0 6 Reduced P64s configuration PMC is not available 0 I O is not a subset of P64 0 5 and 4 Reserved 00b 3 XMC X12d configuration X12d is hard wired 1 I O is X12d compliant 1 2 XMC X8d configuration 1 I O is X8d compliant 0 I O is not X8d compliant N A...

Page 98: ...ilability SSD7 to SSD1 are not supported 0 Hardware Secure Erase not available 0000000b 0 SSD0 availability 0 Hardware Secure Erase not available 1 Hardware Secure Erase available 1 6 34 UART Enable Register 0x6B8 COM3 is connected to the BMM only and has no transceiver associated with it Bits Read Write Description Default 7 to 3 Read only COM8 to COM4 UART enable COM8 to COM4 UARTs are not avail...

Page 99: ...o 2 Read only COM8 to COM3 enable COM8 to COM3 are not available 000000b 1 Read Write COM2 enable 1 COM transceivers enabled 0 COM transceivers disabled 0 0 Read Write COM1 enable 1 COM transceivers enabled 0 COM transceivers disabled 0 6 36 COM Port Mode Register 0x6BC Bits Read Write Description Default 7 to 2 Read only COM8 to COM3 mode COM8 to COM3 are not available 000000b 1 Read Write COM2 m...

Page 100: ...trol disabled 0 0 Read Write COM1 RS485 Auto Direction Control mode 1 COM1 RS485 Auto Direction Control enabled 0 COM1 RS485 Auto Direction Control disabled 0 NOTE Auto Direction Control for a COM port can only be enabled when the corresponding transceiver is in RS422 mode 6 38 COM Port Loopback Enable Register 0x6BE Test software can use loopback mode to test the basic functionality of the transc...

Page 101: ...1 Read only SSD7 to SSD1 cache flush SSD7 to SSD1 are not supported 0 Cache flush not available 0000000b 0 Read Write SSD0 cache flush 0 Cache Flush pin active 1 Cache Flush pin negated 0 6 41 VPX Control Register 0x6C1 The NVMRO Override bit can only be set when the SBC329 is the VPX System Controller the VPX_SYSCON pin is set low Bits Read Write Description Default 7 to 5 Read only Reserved 000b...

Page 102: ...ted 0 XMC1 VPWR rail is 5V 0 5 XMC1 BIST status 1 XMC1 BIST is active 0 XMC1 BIST is not active N A 4 to 0 Reserved 00100b 6 45 Backplane Status Register 0x6CA This register inverts the GA bits so that software can read a true slot number e g the SBC329 in slot 1 only GA0 pulled low results in bits 4 to 0 reading 00001b Bits Description Default 7 SYSCON status 1 SBC329 is fitted into a System Cont...

Page 103: ... 0 3 Boot SPI Flash main write protection status1 2 1 Hardware write protection is active 0 Hardware write protection is not active N A 2 Boot SPI Flash recovery write protection status1 2 1 Hardware write protection is active 0 Hardware write protection is not active N A 1 NVRAM write protection status5 1 Write protection is active 0 Write protection is not active N A 0 Serial EEPROM DIP switch w...

Page 104: ...n2 1x Active boot ROM is located on the test card Abaco only 00 Active boot ROM is the Main on board ROM 01 Active boot ROM is the Recovery on board ROM N A 4 SPD location3 1 SBC329 booted using SPD EEPROM s located on the TAC 0 Board booted using SPD EEPROM s located on board N A 3 Ethernet configuration ROM location4 0 Board booted using on board Ethernet configuration EEPROM 0 2 to 0 Reserved 0...

Page 105: ...ace J15 J16 XMC site P5 on rear of PWB Test Access Card Figure 7 1 Front Connector Positions and Numbering NOTE The SBC329 s guide pin receptacles are unkeyed by default but may be keyed to customer requirements Contact Abaco for more details J16 J15 P0 Upper Key Lower Key P1 P2 I A 1 1 1 16 16 8 A1 F1 A19 F19 A1 F1 A19 F19 ...

Page 106: ...106 SBC329 3U VPX Single Board Computer Publication No SBC329 HRM 1 Figure 7 2 Rear Connector Position and Numbering P5 1 2 80 79 ...

Page 107: ...VS2 None VS1 VS1 VS1 2 VS2 VS2 VS2 None VS1 VS1 VS1 3 VS3 VS3 VS3 None VS3 VS3 VS3 4 NVMRO SYSRESET GND N12V_AUX GND SM3_DATA SM2_CLK 5 SM1_DATA SM0_CLK GND P3V3_AUX GND GA4 GAP 6 GA0 GA1 GND P12V_AUX GND GA2 GA3 7 N C N C GND JTAG_TDI JTAG_TDO GND N C 8 GND N C N C GND REFCLK_P REFCLK_N GND 7 1 2 Backplane J0 Table 7 3 J0 Pin Assignments Fin A B C D E F G H I 1 VS2 VS2 VS2 VS2 None VS1 VS1 VS1 VS...

Page 108: ..._RXP ETH1_2N ETH1_RXN GND ETH1_3P ETH1_TXP ETH1_3N ETH1_TXN GND 7 1 4 Backplane J1 Table 7 5 J1 Pin Assignments Fin A B C D E F G H I 1 PCIE_DP01_RX0P PCIE_DP01_RX0N GND GND PCIE_DP01_TX0P PCIE_DP01_TX0N GND GND GDISC1 2 GND GND PCIE_DP01_RX1P PCIE_DP01_RX1N GND GND PCIE_DP01_TX1P PCIE_DP01_TX1N GND 3 PCIE_DP01_RX2P PCIE_DP01_RX2N GND GND PCIE_DP01_TX2P PCIE_DP01_TX2N GND GND VBAT 4 GND GND PCIE_D...

Page 109: ...XMC_F18 SATA2_RXN GND XMC_C19 SATA2_TXP XMC_C18 SATA2_TXN GND 7 XMC_E01 XMC_D01 GND XMC_B01 XMC_A01 GND COM2_RTS TXD_B GPIO 2 8d 8 GND XMC_E03 XMC_D03 DVI1_DDC_SCL GND XMC_B03 DVI1_DDC_SDA XMC_A03 DVI1_HPD GND 9 XMC_E11 DVI1_DATA_0P XMC_D11 DVI1_DATA_0N GND XMC_B11 DVI1_DATA_1P XMC_A11 DVI1_DATA_1N GND COM2_CTS RXD_B GPIO 3 10 GND XMC_E13 DVI1_DATA_2P XMC_D13 DVI1_DATA_2N GND XMC_B13 DVI1__CLK_P X...

Page 110: ... XMC_F18 SATA2_RXN GND GND XMC_C19 SATA2_TXP XMC_C18 SATA2_TXN GND 7 XMC_E01 XMC_D01 GND GND XMC_B01 XMC_A01 GND GND COM2_RTS TXD_B GPIO 2 8 GND GND XMC_E03 XMC_D03 DVI1_DDC_SCL GND GND XMC_B03 DVI1_DDC_SDA XMC_A03 DVI1_HPD GND 9 XMC_E11 DVI1_DATA_0P XMC_D11 DVI1_DATA_0N GND GND XMC_B11 DVI1_DATA_1P XMC_A11 DVI1_DATA_1N GND GND COM2_CTS RXD_B GPIO 3 10 GND GND XMC_E13 DVI1_DATA_2P XMC_D13 DVI1_DAT...

Page 111: ...s System Controller The state is shown in the FPGA Backplane Status Register offset 0x6CA JTAG_TDO JTAG_TDI The SBC329 does not support boundary scan JTAG_TDI and JTAG_TDO are connected together on the SBC329 to support backplanes where a continuous daisy chain is required REFCLK_P N OpenVPX Reference Clock differential signals Optionally used as 100MHz PCIe REFCLK transmit receive on the SBC329 P...

Page 112: ...ard reset to the SBC329 unless it is masked unmasked by default This pin can also be driven by the SBC329 via the FPGA XMC_xxx XMC I O connections from the J16 connector USB_P2_PWRA B USB3 0 port 2 power USB3_P2_RXP N USB3_P2_TXP N USB3 0 port 2 Receive and Transmit differential pairs BITFAIL Open drain BIT Fail drive for system level BIT Fail COM2_RTS TXD_B Serial COM port 2 Ready To Send flow co...

Page 113: ...3 PCIE_TX3P PCIE_TX3N VPWR 4 GND GND N C GND GND RESET_OUT 5 PCIE_TX4P PCIE_TX4N P3V3 PCIE_TX5P PCIE_TX5N VPWR 6 GND GND N C GND GND P12V_AUX 7 PCIE_TX6P PCIE_TX6N P3V3 PCIE_TX7P PCIE_TX7N VPWR 8 GND GND N C GND GND N12V_AUX 9 Reserved Reserved Reserved Reserved Reserved VPWR 10 GND GND N C GND GND GA0 11 PCIE_RX0P PCIE_RX0N MBIST PCIE_RX1P PCIE_RX1N VPWR 12 GND GND GA1 GND GND PRESENT 13 PCIE_RX2...

Page 114: ...GND GND N C 7 XMC_A07 XMC_B07 N C XMC_D07 XMC_E07 N C 8 GND GND XMC_C08 GND GND XMC_F08 9 XMC_A09 XMC_B09 XMC_C09 XMC_D09 XMC_E09 XMC_F09 10 GND GND XMC_C10 GND GND XMC_F10 11 XMC_A11 XMC_B11 XMC_C11 XMC_D11 XMC_E11 XMC_F11 12 GND GND XMC_C12 GND GND XMC_F12 13 XMC_A13 XMC_B13 XMC_C13 XMC_D13 XMC_E13 XMC_F13 14 GND GND XMC_C14 GND GND XMC_F14 15 XMC_A15 XMC_B15 XMC_C15 XMC_D15 XMC_E15 XMC_F15 16 G...

Page 115: ...s GA 2 0 Geographic Address Used to identify the address of the XMC on a shared I2 C bus GA of 000b for XMC site MBIST XMC Built in Self Test This signal can be held low by the XMC to indicate that it is not yet ready to be enumerated by the root complex PRESENT XMC Present Pulled low by the XMC to allow the SBC329 to detect if an XMC is fitted P3V3_AUX 3 3 V auxiliary supply pins SM_DATA SM_CLK D...

Page 116: ... 5 GHz Configurable as one x8 link or two x4 links One NT port available on either link Video Up to two DVI HDMI One port always available second port build option dependent XMC site x8 PCIe Gen2 capable I O availability is build option dependent up to P2w1X24s X8d X12d available Thermal sensors Board ambient PCIe Switch die temperatures All accessible via BMM Power Supply sensors PMBus compatible...

Page 117: ... up and the total ramp times should be between 20 ms and 150 ms The VPX 12V_AUX supplies are not used on the SBC329 but are connected to the XMC site The values in the table below are inclusive of any ripple on the supplies Table A 2 Voltage Supply Requirements Supply Minimum Nominal Maximum VS1 11 4V 12 0V 12 6V VS2 3 25V 3 3V 3 45V VS3 4 88V 5 0V 5 25V P3V3_AUX 3 14V 3 3V 3 46V P12V_AUX 11 4V 12...

Page 118: ... Total Board Power x4xxxxxxx E3 1505M 25 C Typical 18 63 W estimated 85 C Typical 28 81 W Maximum 56 42 W estimated Maximum 32 1 W Peak 82 12 W estimated Peak TBD W x3xxxxxxx E3 1505L 25 C Typical 16 03 W 85 C Typical 27 48 W Maximum 42 57 W Maximum 35 97 W Peak 52 62 W estimated Peak TBD W A 2 3 Current Consumption SBC329 xxxxxx1xx Variant The following tables show current consumption measured va...

Page 119: ... 20 µA maximum TIP The figures quoted above represent the requirements of the SBC329 under certain conditions When specifying system power supply parameters you are strongly recommended to allow for higher requirements to allow for usage variation and technology insertion This power was measured estimated using the following conditions Table A 10 Power Measurement Conditions Operation Hardware Con...

Page 120: ... C Typical 5 64 A Maximum 9 76 A estimated Maximum TBD A Peak 14 9 A estimated Peak TBD A x3xxxxxxx E3 1505L 25 C Typical 2 4 A 85 C Typical 4 37 A Maximum 6 99 A Maximum 5 67 A Peak 9 A estimated Peak TBD A For current consumption on other rails refer to section A 2 3 A 2 5 XMC Site Current Provision The XMC site can provide the following currents to the XMC Table A 12 XMC Site Current Provision ...

Page 121: ...ity MTBF The following table shows the predicted values for reliability as Mean Time Between Failures MTBF and failures per million hours fpmh for the SBC329 x4411Xxxx see Product Codes for variant details as of 26th June 2017 Table A 14 Reliability MTBF Environment Fail Rate fpmh MTBF Hours Ground Benign 30 C 2 21664 451 134 Ground Fixed 40 C 10 90319 91 716 Ground Mobile 45 C 24 73843 40 423 Nav...

Page 122: ...0 Random 0 04g2 Hz from 20 to 2000 Hz with a flat response to 1000 Hz 6db Octave roll off from 1000 to 2000 Hz 20g peak sawtooth 11 ms duration Up to 95 RH with varying temperature 10 cycles 240 hours Wide temperature Conformally coated for added protection Optional Environmental Stress Screening ESS A 5 2 Conduction cooled Boards Table A 16 Conduction cooled Environmental Specifications Build Sty...

Page 123: ...ld level a maximum CPU operating frequency is achievable For more details contact Abaco and see Appendix B The power dissipation of any XMC fitted should be considered An XMC with high power dissipation could cause the temperature of the SBC329 to rise beyond an acceptable limit The magnitude of the effect of the XMC largely depends on the XMC thermal solution and needs to be considered on a case ...

Page 124: ... Y X24s X8d X12d not available not available not available VITA 61 XMC connectors 1 RS232 2 wire 2 x GPIO 2 RS232 422 485 4 wire not available 3 Not available 4 x GPIO 1 Single BASE T Dual BASE BX 2 Dual BASE T 4 16 GB 32 GB 3 Quad core E3 1505L 2 2 GHz low power 25W 4 Quad core E3 1505M 3 0 GHz standard power 45W 1 Build level 1 2 Build level 2 3 Build level 3 4 Build level 4 5 Build level 5 a Bu...

Page 125: ...n can be altered by the user using BIOS set up screens and these settings are stored in non volatile memory A 7 2 Built In Test BIT probes from the lowest level of discrete on board hardware up to Line Replaceable Unit level within a system ensuring the highest degree of confidence in system integrity BIT includes comprehensive configuration facilities allowing automatic initialization tests to be...

Page 126: ... xxxx VPX3UX601 xxx0x where x any variant Examples of popular variants are shown below SBC329 Variant Compatible RTMs SBC329 14421X106 VPX3UX301 1006 VPX3UX601 10006 SBC329 14411X106 VPX3UX301 1006 VPX3UX601 10006 or VPX3UX601 10016 for BASE BX cable connection SBC329 144111106 VPX3UX301 1106 VPX3UX601 11006 or VPX3UX601 11016 for BASE BX cable connection General information about RTMs can be foun...

Page 127: ...P socket or JTAG header I2C and SPI breakout headers Miscellaneous Abaco only functions links and programming headers Provides a high voltage signal to enable write protection control to the SPD EEPROM device The TAC is available for customer use if required Contact Abaco for more information if required A 10 Development Systems Abaco provides a variety of development chassis See the Abaco website...

Page 128: ...eed versus Maximum Temperature for Processor Option 4 Build Level y Maximum CPU Rating at Maximum Operating Temperature Maximum Operating Temperature at Maximum CPU Rating Heat Dissipation Method Temperature Frequency Frequency Temperature 1 55 C 2 8 GHz estimated 3 0 GHz 55 C estimated 300 lfm blown air 2 65 C 2 5 GHz estimated 3 0 GHz 55 C estimated 3 75 C 2 1 GHz estimated 3 0 GHz 55 C estimate...

Page 129: ... air 2 65 C TBD GHz 2 2 GHz TBD C 3 75 C TBD GHz 2 2 GHz TBD C 600 lfm blown air 4 75 C TBD GHz 2 2 GHz TBD C Card edge 5 85 C TBD GHz 2 2 GHz TBD C NOTES The thermal data for the above table was determined while the units were running multi threaded test software used to stress CPU memory and I O functions simultaneously This test load is generally heavier than a standard embedded application The...

Page 130: ...n Table C 1 Volatile Memory Memory Type Size User Modifiable User Access to Data Function Process to Clear DDR4 SDRAM 16 GB Yes Yes Contains run time data Power off On die processor shared cache 8 MB No No Improved memory performance Power off Chipset CMOS SRAM 256 bytes No Yes Real Time clock data Power off including VBAT supply SRAM 35 Kbit No No Internal FPGA configuration Power off SRAM 1536 b...

Page 131: ...e cleared by any utility capable of writing to I O space EEPROM 256 Kbit Yes Yes Yes PCIe Switch configuration Can be cleared by any utility capable of writing to the Switch local SPI bus Flash 2 x 4 MB No No Yes Ethernet device configuration Can be cleared by any utility capable of writing to the LAN SPI bus FPGA Power Manager N A No Yes N A Power up reset logic glue logic LPC registers timers Wa...

Page 132: ...e Glossary publication number GLOS1 BMM Board Management Microcontroller GB GByte KB KByte lfm Linear feet per minute LRU Line Replaceable Unit MB MByte ME Management Engine PCH Platform Hub Controller PCIe PCI Express POST Power On Self Test RTM Rear Transition Module SKU Stock Keep Unit SPD Serial Presence Detect SSD Solid State Drive TAC Test Access Card SBC328TST TDP Thermal Design Power TPM T...

Page 133: ...y Menu 43 BIT 125 LEDs 74 Block Diagram 46 BMM 69 Board Identification 18 Board Installation 26 Boot Flash 50 Build Levels 122 C Cautions 16 17 23 25 27 30 32 33 43 56 58 61 81 Chassis Ground 26 Configuration Board 23 Link 20 Configuration EEPROM Write Enable 22 Descriptions 21 P3 21 P6 22 Positions 20 Recovery Boot 21 Configuration EEPROMs 22 67 Connecting to SBC329 27 Connectors 105 Backplane 10...

Page 134: ...I O Capabilities 54 I O Modules 126 I2C Bus 66 Identifying Product 18 Inspection 21 Interrupt Controllers 77 Introduction 15 J Jumpers See Configuration Links K Keying 26 L Label 18 LEDs 73 Links See Configuration LPC Bus 63 M Maskable Reset 53 Mechanical Specification 121 Memory 49 Volatility Statement 130 Microprocessor Subsystem 48 MTBF 121 N NVRAM 51 O OpenVPX Compatibility 52 Operating Enviro...

Page 135: ...ry Space Page 84 SATA Port Availability 94 Scratchpad 102 SDD Cache Flush Control 101 R continued Registers continued SSD Availability 98 SSD Erase Control 101 SSD Secure Hardware Erase Capability 98 SSD Status 103 Test 102 Timer 0 Control Status 1 86 Timer 0 Control Status 2 86 Timer 0 Data Bytes 0 to 3 87 Timer 0 IRQ Clear 86 Timer 1 Control Status 1 86 Timer 1 Control Status 2 86 Timer 1 Data B...

Page 136: ...Environment 122 T TAC 127 Technical Specification 116 Technical Support Contact Details 6 Temperature Sensors 70 Thermal Derating 128 Timers 72 Trusted Platform Monitor 63 U Unpacking 18 USB 59 V Vibration 122 Video 62 Volatility Statement 130 Voltage Supply Requirements 117 VPX Interface 52 Connectors 107 W Warnings 16 117 Watchdog 72 Websites 4 5 Wedgelocks 26 Weight 121 X XMC Connectors 24 113 ...

Page 137: ...OVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE ON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED Abaco Systems Information Centers Americas 1 866 652 2226 866 OK ABACO Europe Middle East and Africa 44 0 ...

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