Publication No. SBC329-HRM/1
FPGA Registers 89
6.14 GPIO Registers
The GPIO pin to register bit mapping for the following GPIO registers is as follows:
Table 6-2 GPIO Register Bit Mapping
Bits
Read/Write Description
7 to 4
Read only
Reserved
3 to 0
Read/Write GPIO3 to GPIO0 respectively
6.14.1
GPIO Out Register (0x670)
The value of this register is driven onto the GPIO pins when the direction mode is set
to output. The default is 0x00.
6.14.2
GPIO In Register (0x671)
This returns the status of the GPIO pins, regardless of the direction mode. The
default is 0x00.
6.14.3
GPIO Direction Register (0x672)
Bits 3 to 0 show the direction (input or output) of GPIO3 to GPIO0 respectively, as
follows:
1 = Output
0 = Input (default)
6.14.4
GPIO Interrupt Enable Register (0x673)
Bits 3 to 0 enable interrupts for GPIO3 to GPIO0 respectively, as follows:
1 =Interrupt enabled
0 = Interrupt masked (default)
6.14.5
GPIO Level/Edge Register (0x674)
Bits 3 to 0 set the interrupt detection sensitivity of interrupt pins GPIO3 to GPIO0
respectively (level or edge mode), as follows:
1 =Edge
0 = Level (default)
6.14.6
GPIO Active Low/High Register (0x675)
Bits 3 to 0 set the interrupt detection sensitivity of interrupt pins GPIO3 to GPIO0
respectively (active high/low or rising/falling edge depending on whether the pin is
in level or edge mode), as follows:
1 =Active high/rising edge
0 =Active low/falling edge (default)
