90 SBC329 3U VPX Single Board Computer
Publication No. SBC329-HRM/1
6.14.7
GPIO Both Edges Register (0x676)
Bits 3 to 0 set both-edge mode for interrupt pins GPIO3 to GPIO0 respectively, as
follows:
1 =Both-edge mode enabled
0 =Both-edge mode disabled (default)
When enabled, both-edge mode causes interrupts to be generated on both rising and
falling edges. The GPIO bit must be in edge mode for both-edge mode to work.
6.14.8
GPIO Interrupt Status Register (0x677)
Bits 3 to 0 show the status of interrupt pins GPIO3 to GPIO0 respectively, as follows:
1 =Interrupt pending
0 =No interrupt (default)
Write a ‘1’ to the a
ppropriate bit to clear the corresponding interrupt.
6.14.9
GPIO7 to GPIO0 Availability Register (0x678)
This allows software easily to determine which signals of GPIO7 to GPIO0 are
available. All GPIO signals used shared backplane pins and are only available when
the board is configured with the appropriate build option.
Bits
Description
Default
7 to 4
GPIO7 to GPIO4 are not available
0x0
3
GPIO3 availability (shared with COM2_CTS~/RXD_B signal):
1 =GPIO3 available
0 =GPIO3 not available
N/A
2
GPIO2 availability (shared with COM2_RTS~/TXD_B signal):
1 =GPIO2 available
0 =GPIO2 not available
N/A
1
GPIO1 availability (shared with COM2_RXD/RXD_A signal):
1 =GPIO1 available
0 =GPIO1 not available
N/A
0
GPIO0 availability (shared with COM2_TXD/TXD_A signal):
1 =GPIO0 available
0 =GPIO0 not available
N/A
6.14.10
GPIO15 to GPIO8 Availability Register (0x684)
As GPIO15 to GPIO8 are not supported on SBC329, this register returns 0x00.
