abaco systems SBC329 3U VPX, Hardware Reference Manual

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86 SBC329 3U VPX Single Board Computer Publication No. SBC329-HRM/1
6.11 Timer Registers
6.11.1 Timer 0 Control and Status Register 1 (0x650) and
Timer 1 Control and Status Register 1 (0x658)
Bits Read/Write Description Default
7 Read only Timer IRQ status:
1 = Pending
0 = No interrupt
N/A
6 Read only Reserved 0
5 and 4 Read/Write Clock source select:
00 = Use 2 MHz FPGA clock
01 = Reserved
10 = Reserved
11 = Reserved
00
b
3 Read/Write Timer read selection:
1 = Read timer load value
0 = Read current timer value 0
2 and 1 Read/Write Clock divider (value when 2 MHz clock used):
00 = 1:1 (2 MHz)
01 = 1:2 (1 MHz)
10 = 1:4 (500 kHz)
11 = 1:8 (250 kHz)
00
b
0 Read/Write Enable Timer IRQ:
1 = IRQ enabled
0 = IRQ masked 0
6.11.2 Timer 0 Control and Status Register 2 (0x651) and
Timer 1 Control and Status Register 2 (0x659)
Bits Read/Write Description Default
7 to 5 Read only Reserved 000
b
4 Read/Write Timer read latch select
1 = Latch all timers on read of timer 0 LSB
a
0 = Latch individual timers on read of individual timer LSB
0
3 and 2 Read only Reserved 00
b
1 Read/Write Timer one-shot enable
1 = Timer will count down and stop
0 = Timer will count down and reload at terminal count 0
0 Read/Write Timer enable
1 = Timer enabled
0 = Timer disabled
0
a. Setting this bit in either timer Control and Status Register 2 latches all timers on a read of the timer least
significant byte.
6.11.3 Timer 0 IRQ Clear Register (0x652) and
Timer 1 IRQ Clear Register (0x65A)
Any write to this register clears the timer IRQ.