6. DMA Controller
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An external device or an internal peripheral requests service by activating a channel’s
request input (DRQn). A requester in memory requests service through the DMA
software request register. The requester either transfers data to or retrieves data from
the target.
Programming a DMA Channel
A channel is programmed by writing to a set of registers including requester address,
target address, byte count, and control registers. The address registers specify base
addresses for the target and requester. The byte count registers specify the number of
bytes that need to be transferred to or from the target.
Typically, a channel is programmed to transfer a block of data. Therefore, it is
necessary to distinguish between the process of transferring one byte or word of data
(data transfer) and the process of transferring an entire block of data (buffer transfer).
The byte count determines the number of data transfers that make up a buffer transfer.
After each data transfer within a buffer transfer, the byte count is decremented by 1 and
the requester and target addresses are either incremented, decremented, or left
unchanged. When the byte count expires (reaches -1) the transfer is complete and the
number of bytes transferred is the original byte count +1.
Fly-By and Two-Cycle Bus Cycles
There are two bus cycle options for data transfers, fly-by and two-cycle. Fly-by allows
data transfers to occur in one bus cycle. However, it requires that the requester be in
I/O external to the 386 EX and the target be in memory. The two-cycle option allows
data to be transferred between any combination of memory and I/O through the use of a
4-byte temporary buffer.
The fly-by option performs either a memory write or a memory bus cycle. A write cycle
transfers data from the requester to the target (memory), and a read cycle transfers
data from the target (memory) to the requester. The requester should monitor the bus
cycle signals to determine when to access the data bus.
The two-cycle option first fills the four-byte temporary buffer with data from the source,
then writes that data to the destination. This method allows transfers between any
combination of memory and I/O with any combination of data path widths (8- or 16-bit).
The amount of data and the data bus widths determine the number of bus cycles
required to transfer the data. For example, it takes six bus cycles to transfer four pieces
of data from an 8-bit source to a 16-bit destination: four read cycles to fill the temporary
buffer from the 8-bit source, and two write cycles to transfer the data to the 16-bit
destination. The programmable DMA transfer direction determines whether the
requester or the target is the source or destination.
