Contents
3
4. INTERRUPT CONTROLLER .............................................................................................................31
PROGRAMMABLE REGISTERS...............................................................................................31
INTERRUPT ARCHITECTURE INITIALIZATION REGISTERS (ICW1-ICW4)................34
OPERATIONAL REGISTERS (OCW1-OCW3)..............................................................36
STATUS REGISTERS (IRR, ISR, IPR) .........................................................................37
ADDITIONAL INFORMATION ...................................................................................................38
5. COUNTER/TIMERS...........................................................................................................................39
PROGRAMMABLE REGISTERS...............................................................................................41
COUNT REGISTERS AND COUNT LATCH .................................................................41
STATUS REGISTER ....................................................................................................42
CONTROL REGISTER .................................................................................................43
ADDITIONAL INFORMATION ...................................................................................................44
6. DMA CONTROLLER .........................................................................................................................45
INTEL 386 EX INTERNAL ARCHITECTURE.............................................................................45
DMA IMPLEMENTATION..........................................................................................................47
DMA TRANSFER CYCLES...........................................................................................48
I/O MAPPING ...............................................................................................................48
DMA CONTROLLER OPERATION ...........................................................................................48
PROGRAMMING A DMA CHANNEL ............................................................................49
FLY-BY AND TWO-CYCLE BUS CYCLES....................................................................49
386 EX DMA CONTROLLER REGISTERS ...............................................................................50
PIN MUX CONFIGURATION ........................................................................................51
PERIPHERAL CONNECTIONS AND MASK .................................................................53
CHANNEL 0 REQUESTOR ADDRESS REGISTERS....................................................53
CHANNEL 1 REQUESTOR ADDRESS REGISTERS....................................................55
CHANNEL 0 TARGET ADDRESS REGISTERS ...........................................................56
CHANNEL 1 TARGET ADDRESS REGISTERS ...........................................................58
CHANNEL 0 BYTE COUNT REGISTERS .....................................................................59
CHANNEL 1 BYTE COUNT REGISTERS .....................................................................61
DMA STATUS REGISTER............................................................................................62
DMA COMMAND REGISTERS.....................................................................................63
DMA MODE REGISTERS.............................................................................................64
DMA SOFTWARE REQUEST REGISTER ....................................................................65
DMA SINGLE CHANNEL MASK REGISTER ................................................................66
DMA GROUP CHANNEL MASK ...................................................................................66
DMA BUS SIZE REGISTER..........................................................................................66
DMA CHAINING REGISTER ........................................................................................67
DMA INTERRUPT ENABLE REGISTER.......................................................................68
DMA INTERRUPT STATUS REGISTER.......................................................................68
DMA OVERFLOW ENABLE REGISTER.......................................................................69
7. REAL-TIME CLOCK..........................................................................................................................70
PROGRAMMABLE REGISTERS...............................................................................................70
REGISTER A................................................................................................................72
REGISTER B................................................................................................................73
REGISTER C................................................................................................................73
REGISTER D................................................................................................................74
ADDITIONAL INFORMATION ...................................................................................................74
8. SERIAL CONTROLLER ....................................................................................................................75
ZT 8904 SPECIFICS .................................................................................................................75
ADDRESS MAPPING ...................................................................................................76
INTERRUPT SELECTION ............................................................................................76
HANDSHAKE SIGNALS ...............................................................................................76
RS-485 OPERATION....................................................................................................77
SERIAL CHANNEL INTERFACE ..................................................................................77
