Zenith Z-100 Series, Техническое руководство

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Page 2.13
PROG R A M M ING INFORMATION
8253 Timer Status Port (FB)
Port
A ddress D 7
D6 D5 D4
D3 D2 D1
DO
FB
Timers
Timer 1
The timer circuitry consists of an 8253 timer IC and several
other IC's. (See the Timer Port Address Block Diagram.) The
8253 has three channels. Each channel has a input clock
( — CLK) and an output (OUT). The CLOO and CLK2 inputs
are tied to a 250 kHz (4 p,S) clock. The CLK1 input is tied
to the output of channel 0, and thus channels 0 and 1 are
cascaded.
Outputs OUTO and OUT2 produce the timer interrupt input
to the 8259. A latch is provided which can be read to deter-
mine which of the channels caused the interrupt (TMRSTAT).
Outputs of these latches are OR'ed together to produce the
interrupt input to the 8259.
To find out which timer caused an interrupt, the timer status
port must be read. A high level on either the Timer 0 or Timer
1 bit indicates that the corresponding timer has had a positive
transition on its OUT signal. In order to detect the next transi-
tion on the OUT signal, the latch should be cleared by writing
a zero to the appropriate bit position in the timer status port.
The 8253 data sheet is supplied in the Appendices portion
of this documentation. The following chart is provided for the
convenience of those who may already be familiar with the
8253 device.