Zenith Z-100 Series, Техническое руководство

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CIRCUIT DESCRIPTION
I/O Port Decoder
T he heart of the I/O port decoder is U179, a 256 x 4 b i t
PROM. Depending on which main board port the CPU addres-
ses, U179 enables U159 or U157, respectively a 3-to-8 line
decoder and a dual 2-to-4 line decoder.
To address one of these ports (OEOH through OFFH), the CPU
first places the appropriate port address on the inputs of U179,
AO through A7. This address comes from the S-100 address
lines, AO-A7, through octal buffer U181.
When the address lines have stabilized, the CPU enables
U179 by asserting pin 13, the IO line. This signal comes from
U224C pin 10 and goes low whenever the CPU asserts the
S-100 slNP or sOUT lines. Once lO is asserted, U179 de-
codes the address at its inputs and selects either U159 or
U157.
For example, it selects U159 for a memory control latch opera-
tion by bringing U179 pin 12 to logic 0. U159 then decodes
the lower three bits of the address bus coming in at pins 1,
2, and 3 to assert pin 11, which carries the MEMCTRLCS
signal.
U159 also selects the following ports:
TMRSTATCS. This is the timer status port at U160.
HI-ADCS. This line controls the extended addressing
latches.
SWAPCS. This line connects to the processor swap port.
DWSEL. This line controls the power-up reset configura-
tion port at U239.