Zenith Z-100 Series, Техническое руководство

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CIRCUIT DESCRIPTION
The third RAS cycle of the video timing cycle is reserved for
the CPU. If the CPU doesn't attempt to read or write memory,
RAS will not assert during the time marked "CPU." If the CPU
does attempt to read or write memory RAS will assert and
the memory access can take place. Note that during CPU
RAS time, VIDSTRB (U376 pin 17) does not pulse. This pre-
vents the addressed memory location from being latched into
U332, U302, and U311; keeping unwanted noise off the dis-
play.
If the CPU attempts to access video memory during the CRT-
C portion of the cycle, the arbitration circuits places a logic
zero on P305 pin 62. This logic zero couples to the CPUs
READY line which puts the CPU into a wait state. The CPU
ceases activity until the "CPU" RAS cycle begins. At this time,
P305 pin 62 goes high to activate the CPU.
Obviously, the CPU processing time will slow down if it per-
forms a lot of reading and writing to video RAM. However,
the video arbitration circuits do not slow down the CPU for
non-video operations (such as I/O and system memory acces-
ses). As long as the CPU isn't accessing the video circuits,
P305 pin 62 remains high and the CPU operates at full speed.
Now for a closer look at the video arbitration circuits.
Video Arbitration
The video arbitration circuits determine if the CPU is request-
ing access to the video RAM. If the CRT-C is not using the
RAM, it gives control to the CPU. However, the CRT-C always
has priority.
As mentioned previously, the CPU requests control of the
VRAM by asserting RSEL, GSEL, or BSEL at U371. This as-
serts CRTRAMSEL which couples through U372 pin 3 to put
the CPU into a wait state after the CPU finishes the 2nd pro-
cessor cycle.