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CIRCUIT DESCRIPTION
Parallel Port
General
The parallel port is designed around a 68A21 peripheral inter-
face adapter (PIA) at U114. This IC performs three functions:
(1) it operates as a printer port; (2) it serves as a port for
a light pen; and (3) it couples the video board vertical retrace
signal to the CPU.
The CPU accesses U114 for programming or data transfer
through U135 and U136. At the same time, it chip-selects
U114 by asserting the 6821CS control line from the I/O port
decoder. The CPU also asserts address lines BAO and BA1
(pins 36 and 35) to select the correct internal register.
The enable line, E-CLK, comes from the E-clock logic circuits
described previously and provides timing to U114. All other
signals to the PIA are referenced to either the rising or falling
edges of this line.
The CPU asserts the OUT line on pin 21 of U114 when the
computer needs to write to the PIA. In all other cases, the
PIA is in the read mode when enabled. Actual data transfer
between the CPU and PIA takes place when the CPU asserts
WO at U136 pin 1 for a write, or DBIN at U175 pin 10 for
a read. The other connections to U114 are covered in follow-
ing sections. (For a complete description of the internal opera-
tion of the PIA, see the data sheets in Appendix C.)
Содержание Z-100 Series
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