Zenith Z-100 Series, Техническое руководство

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Page 10.8
GENERAL INFORMATION
The KILL P A RITY option disables the parity checking cir-
cuitry. This option is enabled when the system writes a 0 to
bit 5 of the MEMCTL port. It also clears a parity error by
first writing a 0 to bit 5 of the port and then a 1 to bit 5 of
the port.
Timer
The 8253 timer has three channels. (See Pictorial 10-1). Each
channel has an input (CLK), and an output (OUT). As shown,
channels 0 and 1 are cascaded. CLKO and CLK2 are tied
to a 250 kHz (4 p.s) clock, and the CLK1 '.nput is tied to the
output of channel 0.
The two outputs that are available externally are OUTO and
OUT2. These are ORed together to produce the timer interrupt
input of the 8259. A latch is provided which, when read by
software, determines which of the channels caused the inter-
rupt (TMRSTAT).
TMRSTAT must be cleared by the program after it is read.
Bit 0 of TMRSTAT corresponds to OUTO, and bit 1 is OUT2.
The appropriate latch is cleared by writing a 0 to that bit of
TMR STAT.
250 KHz (4ps)
8253
T IMER
8253
T IMER
CH 1
CH 0
CLK 0
OUT 0
CLK 1
CLK 2
OUT 2
LATCH
DATA
CH 2
CLK
I NT.
Pictorial 10-1