Page 2.11
PROG R A M M ING INFORM ATION
Memory Control Latch Port (FC)
This port controls the configuration of memory, both ROM and
RAM. It also provides an option for checking RAM parity. The
options, which affect how the ROM is addressed, are enabled
by writing to the memory control latch (MEMCTL) port.
Port
Address
D 7
D6
D5
D4
D3
D2
D 1
DO
FC
RAM
Configurations
)
ROM
Configurations
Zero Parity
Kill Parity
The following chart shows which port bits control the various
RAM configurations.
BITS
DEF I N ITION
1,0
00
=
Option 0
10
=
Option 2
01 =
Option1
11 =
Option3
Option 0, the power-up master reset configuration, pro-
vides contiguous addressing; from 0 to 192 K.
Option 1, swaps the RAM block from 0 to 48 K with the
block at 64 to 112 K.
Option 2, swaps the RAM block from 0 to 48 K with the
block at 128 to 172K.
Option 3, swaps the RAM block from 4 to 60 K with the
block at 68 to 124 K.
Содержание Z-100 Series
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