Page 10.7
GENERAL INFORMATION
RAM normally consists of from one to three banks of 64K
bytes. This provides from 64 to 192K bytes of memory.
The RAM address configuration depends on the map control
bits in MEMCTL. Bit 0 is MAPSELO and bit 1 is MAPSEL1.
The following chart shows which port bits control the various
RAM configuration.
BITS
D EFI N ITION
00
=
Option 0
10
=
Option 2
01 =
Option1
11
=
Option3
1,0
Option 0, the power-up and master reset configuration,
provides contiguous addressing; from 0 to 192K.
Option 1 swaps the RAM block from 0 to 48K with the
block at 64 to 112K.
Option 2 swaps the RAM block from 0 to 48K with the
block at 112 to 160K.
Option 3 swaps the RAM block from 4 to 60K with the
block at 68 to 124K.
Parity
Parity consists of a parity bit for each byte in RAM. This adds
one, two, or three 64K-bit chips (depending on how much
RAM is installed: 64K, 128K, or 192K) and the associated
support circuitry.
RAM parity has two control options: ZERO PARITY and
KILL PARITY. The ZERO PARITY option sets parity to the
zero state regardless of the data pattern that was written, and
forces a parity error to check the parity logic. The option is
activated when the system writes a 0 to bit 4 of the Memory
Control Latch (MEMCTL) port.
Содержание Z-100 Series
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