CIRCUIT DESCRIPTIONS
D60WLCD - 923-03486
3-13
094A - SERVICING
2) SYNC Counter
The H and V sync signals selected by the HV sync signal
processing block described previously are sent to the
SYNC counter block next. The SYNC counter block counts
the frequency of the input H and V sync signals. The
SYNC counter block counts the H sync signal input
during a certain period (.5ms) based on the clock
obtained by the internal VCO from the 4MHz crystal
oscillator or ceramic oscillator connected to EXTCLK/
XTAL (Pin 20), and returns these results to the H-
NUMBERH/L status registers in 10 bits.
When the H sync signal is not input, H-NUMBER-H/L is
0 or 1. For the V sync signal, the number of reference
clock (31.25kHz) pulses during 1 V cycle is counted,
and these results are returned to the V-NUMBER-H/L
status registers in 10 bits.
When the V sync signal is not input, the count that
matches the frequency selected by VFREQ (I2C bus) is
returned to VNUMBER-H/L. The SYNC count values and
conversion formulas for each H and V sync signal are
shown below.
Note that a 4MHz external clock can be input to EXTCLK/
XTAL (Pin 20) via a capacitor by setting CLK_SEL (I2C
bus).
A dummy sync can be output by setting SELDUM (I2C
bus). Select the dummy sync frequency with HFREQ and
VFREQ( I2C bus). However, note that when the dummy
sync is selected, the SYNC counter does not operate
even if H and V sync signals are input.
H sync signal fH [kHz]
Count value [HEX]
15.73
4F
31.5
9D
33.75
A8
45
E1
V sync signal fV [kHz]
Count value [HEX]
60
208
50
271
Count value ([DEC] / [HEX]) = fH # 5ms
Count value ([DEC] / [HEX]) = 1/(fV # 32ns)
SYNC values and formulas
H_IN
Sync on Y/Sync on GREEN
Clamp Pulse
T1: 0.7 s (typ.)
T2: 0.4 s (typ.)
T1 + T2: 1.0 to 1.4 s (max.)
T1
Video Interval
T2
Connect a resistor (such as a metal film resistor) with an error of 1% or less to IREF (Pin18).
3) Notes on Operation
• Processing for unused pins. OPEN: Pins 1 to 3, 7, 8,
33 to 35, 38, 39, 41 to 43, 46 and 47 Connected to
GND via a capacitor and resistor: Pins 4, 5, 10, 11, 36,
37, 44 and 45 (See each H and V input and the
Application Circuit). This is to prevent the SYNC counter
from misoperation.
• Input the H and V inputs at sufficiently low
impedance.
• Internal clamp timing. The internally generated clamp
pulse follows the timings T1 and T2 shown below. Input
H_IN and Sync on Y/Sync on Green so that the clamp
pulse does not overlap the video interval to prevent
clamping error.
Содержание D60WLCD Series
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