Zenith D60WLCD Series, Руководство по обслуживанию

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CIRCUIT DESCRIPTIONS
D60WLCD - 923-03486
3-20
094A - SERVICING
In the case of YUV input signals, blanking levels for U
& V correspond to the midlevel analog input. To handle
these signals the clamping range should be centered
on the midlevel output code of the A/D.
The clamp code is 8 bits wide and spans 128 ADC output
codes (a 2 LSB change to clamp code corresponds
nominally to 1 LSB change in ADC output code). The
programmed clamp code is independent of the PGA
setting (see later). This ensures independent
brightness/clamping control.
The clamp pulse defines the timing window during which
the clamp circuit is internally enabled, and is either
generated externally and supplied to the device, or it
can be internally generated. In the latter case the user
can program both the position and width of the clamp
pulse with respect to the horizontal sync (HS) input.
3) Programmable Gain Amplifier (PGA)
Each video channel is passed through a programmable
gain amplifier, to provide a full-scale signal to each A/
D. The user can change this gain via register
programming. Any gain change becomes effective
immediately. The range of the PGA is such that an input
ac range from 0.4Vpp to 1.2Vpp can be scaled to ADC
full scale, by maximum gain and minimum gain settings
respectively.
The PGA is split into a 6 bit coarse gain control and 5
bit fine gain control. Their combination leads to a
PGA resolution of better than 1 LSB on the ADC output
code. The bandwidth of the PGA is constant, resulting
in a constant analog video input bandwidth. The coarse
PGA, with its 64 settings, covers a 4/3x to 4x gain
change, used for a 0.4V (0.4Vpp x 4 = 1.6Vpp) resp.
1.2Vpp (1.2Vpp x 4/3 = 1.6Vpp) input range swing.
While an amplifier with variable gain implements the
coarse PGA, the fine PGA is implemented by slightly
changing the top & bottom reference levels that are
also independently controllable for each ADC channel.
The fine range, with its 32 settings, covers a range of
16 LSB’s. The fine and coarse PGA settings can be
combined into a single PGA gain formula as follows:
GAIN = (4/3 + C/24)(1 +(F-15)/512)
Where C is the coarse gain setting (0..63) and F the
fine gain setting (0..31).
4) A/D Converter
The A/D converter is based on the core used in the
TLV5580 (single 8-bit 80 MSPS A/D). The switched-
capacitor single- pipeline CMOS architecture combines
excellent signal-to-noise characteristics with a very wide
3dB analog input bandwidth of typ. 500 MHz. The A/
D block contains an internal reference voltage generator,
providing stable bottom and top references derived
from an internal bandgap reference. The reference
voltages are made available externally. THS8083
supports both A/C and D/C coupled input (clamping
disabled). In the latter case, the externally made
available references can be used to level-shift the input
signal.
The A/D converter is guaranteed up to 80 MSPS
(THS8083) or 95 MSPS (THS8083-95) with no missing
codes. The sampling clock of the A/D converter is either
fed from external or generated internally by the PLL.
5) Output formatter
This block enables either a 4:4:4 24-bit output or 4:4:4
48-bit output at half the pixel clock or a 4:2:2 16-bit
output, useful for YUV digitizing (ITU.BT-601 style).
In the latter case 8-bit is used for the Y output, while
a 2nd 8 bit port is used alternately for Cr and Cb. As
per ITU BT-601, Cb is the first video data word for
each line, as shown in Figure.
The first color sample after an incoming HS will be Cb..
The output signal DHS is synchronized to the first pixel
of a line and can therefore be used to uniquely identify
Cb from Cr output data in downsampled modes.
Y
3 Channels
Output formatter
combines Cb, Cr on
a single output bus
2 Channels
Output Format
Sampling Format
Cb
On Ch1 bus
A output
Cb (or B-Yor U)
Cr Cb Cr Cb
t
Other Outputs
Hi-Z
On Ch2 bus
A output
Y
Y
Y Y Y Y
Cr (R-Y or V)
Formatting