
CIRCUIT DESCRIPTIONS
D60WLCD - 923-03486
3-18
094A - SERVICING
ANALOG TO DIGITAL CONVERTER (THS8083)
FEATURES
1) Analog Channels
• Three digitizing channels, each with independently
controllable Clamp, PGA and ADC.
• Clamp: 256-step programmable RGB or YUV clamp-
ing during external or internal clamp timing win-
dow
• PGA: 6 bit coarse / 5 bit fine programmable gain
amplifier
• ADC: 8 bit 80MSPS (THS8083) or 95MSPS
(THS8083- 95) A/D converter
• Composite Sync: Integrated Sync-on-green / Sync
onluminance extraction
• Support for AC and DC-coupled input signals
2) PLL
• Fully integrated digital PLL (including loop filter)
for pixel clock generation
• 10-80 MHz (THS8083) or 10-95 MHz (THS8083-
95) pixel clock generation from reference Input
• Adjustable PLL loop bandwidth for minimum jitter
or fast acquisition/wide capture range modes
• 5-bit programmable sub-pixel accuracy position-
ing of sampling Phase.
• Noise gates on HS input to avoid false PLL updat-
ing
3) Output Formatter
• Single and double pixel width output data bus for
reduced board clock frequency & EMI
• Support for 4:4:4 and 4:2:2 (ITU.BT-601 style)
output modes to reduce board traces and video
ASICs
• Dedicated DATACLK output for easy latching of
output data
4) System
• Industry-standard normal/fast I2C Interface with
register readback capability
• Support for input format detection via integrated
monitoring of HS,VS and pixelclock frequencies
• Support for multi-device operation (master/slave
operation for SXGA resolution)
• Space-saving TQFP-100 pin package
• Thermally-enhanced PowerPAD package for reduced
heat dissipation
BLOCK DIAGRAM
HS
LOCK
VCM
CH2_IN
CS
AVDD_CH2_3
AVSS_CH2_3
CH3_IN
AVSS_REF
VS
EXT_CLP
EXT_ADCCLK
PFD_FREEZE
AVDD_CH1
AVSS_CH1
CH1_IN
VMID
AVDD_REF
VREFTO_CHn
/OE
VREFBO_CHn
CH1A[7..0]
CH1B[7..0]
CH2A[7..0]
CH2B[7..0]
CH3B[7..0]
CH3A[7..0]
VSS
DVDD
DVSS
DATACLK1
SCL SDA
I2CA
/RESET
SCAN_TEST
DHS
DVSS_PLL
ADCCLK2
THS8083
DT0CLK3
DVDD_PLL
AVDD_PLL
AVSS_PLL
v3.0
XTL
1
XTL
2
PLL
CLP
ADC3_OUT
ADC2_OUT
ADC1_OUT
Slicer
Clamp
Bandgap
Ref.
Programmable
Variable
Gain Amplifier
Clamp
Clamp
Programmable
Variable
Gain Amplifier
Programmable
Variable
Gain Amplifier
ADC(R)
ADC(R)
ADC(R)
Ref. Gen.
Ref. Gen.
Ref. Gen.
Output
Formatter
LEGEND
SIGNAL
CONTROL
TEST
POWER/GND
Control
Interface
(I2C)
Clamp
Timing
Gen.
Noise
Gates
Содержание D60WLCD Series
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Страница 69: ...D60WLCD 923 03486 5 3 094A EXPLODED VIEWS D60WLCD Main PCB Layout...
Страница 70: ...D60WLCD 923 03486 5 4 094A EXPLODED VIEWS D60WLCD Power PCB Layout Power Ballast Interface...
Страница 71: ...D60WLCD 923 03486 5 5 094A EXPLODED VIEWS D60WLCD Digital PCB Layout...
Страница 72: ...D60WLCD 923 03486 5 6 094A EXPLODED VIEWS D60WLCD Drive PCB Layout...
Страница 73: ...D60WLCD 923 03486 5 7 094A EXPLODED VIEWS D60WLCD Chroma PCB Layout...
Страница 74: ...D60WLCD 923 03486 5 8 094A EXPLODED VIEWS D60WLCD Tuner PCB Layout...
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