CIRCUIT DESCRIPTIONS
D60WLCD - 923-03486
3-16
094A - SERVICING
DIGITAL BLOCK
RISC MICROCONTROLLER (KS32C5000)
DESCRIPTION
Peripheral functions include two HDLCs, two UART
channels, 2-channel GDMA, two 32-bit timers, and 18
programmable I/O ports. On-board logic includes an
interrupt controller, DRAM controller, and a controller
for ROM/SRAM and flash memory. The System Manager
includes an internal 32-bit system bus arbiter and an
external memory controller.
FEATURES
1) Architecture
• Integrated system for embedded Ethernet appli-
cations
• Full 16/32-bit RISC architecture
• Big-Endian memory system
• ARM7TDMI core
• JTAG-based debug solution
• Boundary scan
2) System Manager
• 8/16/32-bit external bus support for ROM/SRAM,
flash memory, DRAM, and external I/O
• One external bus master with bus request/acknowl-
edge pins
• Support for EDO DRAM
• Programmable access cycle (0–7 wait cycles)
• Four-word depth write buffer
• Memory-to-peripheral DMA interface
3) Unified Instruction/Data Cache
• Two-way, set-associative, unified 8-Kbyte cache
• Support for LRU (least recently used) protocol
• Cache is configurable as internal SRAM
4) I2C Serial Interface
• Master mode operation only
• Baud rate generator for serial clock generation
5) Ethernet Controller
• DMA engine with burst mode
• DMA Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
• MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes Rx)
• Data alignment logic
• Endian translation
• 100/10-Mbit per second operation
• Full compliance with IEEE standard 802.3
• MII and 7-wire 10-Mbps interface
• Station management signaling
• On-chip CAM (up to 21 destination addresses)
• Full-duplex mode with PAUSE feature
• Long/short packet modes
• PAD generation
6) HDLCs
• HDLC protocol features:
– Flag detection and synchronization
– Zero insertion and deletion
– Idle detection and transmission
– FCS encoding and detection (16-bit)
– Abort detection and transmission
• Address search mode (expandable to 4 bytes)
• Selectable CRC or No CRC mode
• Automatic CRC generator preset
• Digital PLL block for clock recovery
• Baud rate generator
• NRZ/NRZI/FM/Manchester data formats for Tx/Rx
• Loop-back and auto-echo modes
• Tx/Rx FIFOs have 8-word (8 # 32-bit) depth
• Selectable 1-word or 4-word data transfer mode
• Data alignment logic
• Endian translation
• Programmable interrupts
• Modem interface
• Up to 4 Mbps operation using an external clock
• Up to 2 Mbps rate with a 32-MHz for FM encoding
using DPLL
• Up to 1 Mbps rate with a 32-MHz for NRZI encod-
ing using DPLL
• HDLC frame length based on octets
• 2-channel DMA engine for Tx/Rx on each HDLC
7) DMA Controller
• 2-channel General DMA for memory-to-memory,
memory-to- UART, UART-to-memory data transfers
without CPU intervention
• Initiated by a software or external DMA request
• Increments or decrements source or destination
address in 8-bit, 16-bit or 32-bit data transfers
• 4-data burst mode
8) UARTs
• Two UART (serial I/O) blocks with DMA-based or
interruptbased operation
• Support for 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit and receive
• Programmable baud rates
• 1 or 2 stop bits
Содержание D60WLCD Series
Страница 64: ......
Страница 65: ......
Страница 66: ......
Страница 69: ...D60WLCD 923 03486 5 3 094A EXPLODED VIEWS D60WLCD Main PCB Layout...
Страница 70: ...D60WLCD 923 03486 5 4 094A EXPLODED VIEWS D60WLCD Power PCB Layout Power Ballast Interface...
Страница 71: ...D60WLCD 923 03486 5 5 094A EXPLODED VIEWS D60WLCD Digital PCB Layout...
Страница 72: ...D60WLCD 923 03486 5 6 094A EXPLODED VIEWS D60WLCD Drive PCB Layout...
Страница 73: ...D60WLCD 923 03486 5 7 094A EXPLODED VIEWS D60WLCD Chroma PCB Layout...
Страница 74: ...D60WLCD 923 03486 5 8 094A EXPLODED VIEWS D60WLCD Tuner PCB Layout...
Страница 76: ......