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CIRCUIT DESCRIPTIONS
D60WLCD - 923-03486
3-12
094A - SERVICING
[MAT_OUT = 3: GBR / YCbCr]
Y = 0.3R + 0.59G + 0.11B
Cb = 0.564 (–0.3R – 0.59G + 0.89B)
Cr = 0.713 (0.7R – 0.59G – 0.11B)
In addition, the IN1 and IN2 systems support D3 input
pins. This is selected by SELSTB_1 and SELSTB_2 (I2C
bus). The control line input voltage of each L1, L2, L3
and SW pin is returned to the status register by a ternary
or binary value.
Next, the HV sync signal processing block is described
below. Existence distinction is first performed to
determine whether the selected sync signals are input
from H and V, and these results are sent as the existence
status to the EV and EH status registers. On the other
hand, polarity-matched H and V that passed through
the polarity identification circuit are input to the
priority ranking circuit.
When inputting composite sync (CS), input to the H
input pin of each input system. After passing through
the polarity identification circuit, V sync separation
is performed and the signal is input to the priority
ranking circuit.
When inputting Sync on Y or Sync on Green, input to
the number 3 pin of each input system. After passing
through HYSW, the signal is amplified by 6dB and
output to YG_OUT (Pin 15). This output is returned to
YG_IN (Pin 16) via a sync tip clamping capacitor, sync
separation is performed, and the signal is input to the
priority ranking circuit. This route can also be used
during CS signal input by setting HYSW (I2C bus) to 1.
In addition, sync identification is performed to
determine whether the input signal from YG_IN (Pin
16) is Tri-level sync, and these results are returned to
the 3STATE status register. In this manner, the
respective signals are input to the priority ranking
circuit, and the output sync signal is determined by
the EV and EH status. The priority ranking is as follows.
The TV set should be designed so that one of the
following three points are met.
1. When both H and V exist at the H and V pins, these
signals are selected with the highest priority. $ EH =
1, EV = 1.
2. When CS exists at the H pin and there is no input at
the V pin, CS is selected. EH = 1, EV = 0.
3. When Y or GREEN exists at the number 3 pin and
there is no input at the H and V pins, Y or GREEN is
selected. EH = 0, EV = 0.
After the HV output is determined, the H sync signal
pulse width is adjusted by H_WIDTH (I2C bus), and
then the H sync signal is output together with the V
sync signal to SEL_OUT.
VIDEO/SYNC SELECTOR
DESCRIPTION
The CXA2151Q is a bipolar IC developed for multi scan
TVs, and incorporates a four system video switch
(including HV sync signal processing) and a YCbCr
output matrix circuit.
FEATURES
• Supports the I2C bus
• Supports multi scan
• Four system video switch (of which two systems
support D3 pins)
• Matrix circuit
• Each YCbCr output can be switched between 0dB,
6dB (gain adjustable) and mute.
• Sync signal automatic identification circuit (with
fixed mode)
• Sync separation circuit (supports HD)
• HD Tri-level sync identification circuit
• Sync signal frequency counter (both H and V)
• Dummy sync output
OPERATION
1) Programmable Matrix Selector
The CXA2151Q has a built-in four system video switch
which can be selected by INPUT_SEL (I2C bus). YCbCr,
HD YPbPr, GBR and the respective HV sync signals can
be input to each system. Horizontal scanning line
frequencies from 15 to 45kHz can be input as the range
which supports multi scan.
The selected signals are output from SEL_OUT (Pins
22, 23, 25, 26 and 27), respectively. The output
amplitude at this time can be selected by GAIN_SEL
(I2Cbus), but when GAIN_SEL is set to 0, the gain can
be adjusted by YGAIN, CBGAIN and CRGAIN (I2C bus).
HV sync signal input supports both positive and
negative polarity. Select MAT_OUT (I2C bus) as follows
according to the input.
• Select THROUGH mode during YCbCr input.
• When YPbPr or GBR are input, select the mode that
converts these signals to YCbCr.
The matrix conversion formulas are shown below.
[MAT_OUT = 1: YHDPbPr / YCbCr]: CCIR protocol
Y = YHD + 0.094Pb + 0.196Pr
Cb = 0.564 (1.762Pb – 0.196Pr)
Cr = 0.713 (–0.094Pb + 1.379Pr)
[MAT_OUT = 2: YHDPbPr / YCbCr]: BTA protocol
Y = YHD + 0.068Pb + 0.191Pr
Cb = 0.564 (1.758Pb – 0.191Pr)
Cr = 0.713 (–0.068Pb + 1.385Pr)
Содержание D60WLCD Series
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