Yamaha DM 1000, Руководство по обслуживанию

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55
DM1000/MB1000/SP1000
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
COREV
DD
/WAIT
DB15
DB14
DB13
DB12
DB11
DB10
DB9
IOV
DD
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
V
SS
COREV
DD
GPIO0
FPDAT11
FPDAT10
FPDAT9
FPDAT8
V
SS
FPSHIFT
IOV
DD
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
FPLINE
FPFRAME
V
SS
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Power 3.3V
Wait signal
Data bus
Power 3.3V
Data bus
Ground
Power 3.3V
General purpose input/output
Panel data
Ground
Shift clock
Power 3.3V
Panel data
Line pulse
Frame pulse
Ground
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80 COREV
DD
DRDY
LCDPWR
TESTEN
CNF4
CNF3
CNF2
CNF1
CNF0
V
SS
CLKI
IOV
DD
AB15
AB14
AB13
AB12
AB11
AB10
AB9
V
SS
COREV
DD
AB8
AB7
AB6
AB5
AB4
AB3
AB2
AB1
AB0
BCLK
V
SS
/RESET
/CS
/BS
/RD
/WE0
/WE1
RD//WR
V
SS
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Power 3.3V
TFT/D-TFD display enable
LCD power control
Test enable input
Configure the S1D13704
Ground
Input clock
Power 3.3V
Address bus
Ground
Power 3.3V
Address bus
System bus clock
Ground
Reset
Chip select signal
Bus start signal
Read signal
Write enable signal for the lower data byte
Write enable signal for the upper data byte
Read/write signal
Ground
S1D13704F00A100 (X3498A00) LCDC (LCD Controller)
MAIN: IC027
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDA/CDOUT
AD0//CS
/EMPH
RXP
RXN
VA+
AGND
FILT
/RST
RMCK
RERR
ILRCK
ISCLK
SDIN
I/O
I
O
I
I
I/O
I
O
O
I/O
I/O
I
Serial control data I/O (I
2
C) / data out (SPI)
Address bit 0 (I
2
C) / Control port chip select (SPI)
Pre-emphasis indicator output
Differential line receiver inputs
Positive analog power supply (+5V)
Analog ground
PLL loop filter
Reset input
Input section recovered master clock output
Receiver error indicator
Serial audio input port left/right clock input or output
Serial audio input port bit clock input or output
Serial audio input port data input
15
16
17
18
19
20
21
22
23
24
25
26
27
28 TCBL
OSCLK
OLRCK
SDOUT
/INT
U
OMCK
DGND
VD+
H//S
TXN
TXP
AD1/CDIN
SCL/CCLK
I/O
I/O
I/O
O
O
I/O
I
O
O
O
I
I
Transmit channel status block start
Serial audio output port bit clock input or output
Serial audio output port left/right clock input or output
Serial audio output port data output
Interrupt output
User data
Output section master clock input
Digital ground
Positive digital power supply (+5V)
Hardware or software control mode select
Differential line driver outputs
Address bit 1 (I
2
C) / Serial control data in (SPI)
Control port clock
CS8420 (XW559A00) SRC (Sample Rate Converter)
MAIN: IC601, 602