Xycom XVME-212, Руководство пользователя

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XVME-2 12 Manual
August, 1989
8-l1: Change Register n Status
Change Register Status bits:
Bit 8 -- Status of Change Register 0
Bit 9 -- Status of Change Register 1
Bit 10 -- Status of Change Register 2
Bit 11 -- Status of Change Register 3
When the scanner detects a bit set in a Change Register, it will set the
appropriate above bit to 1.
These bits are reset to zero when the
corresponding Data Register is read. These bits may be polled to quickly
determine whether any Change Registers have bits set. These bits are not
conditioned by any one of the interrupt enable bits 4-7.
12-15:
Not used.
3.5.2
Generating VMEbus Interrupts
Bits 4-7 of the Status/Control Register are individually ANDed with bits 8-11. The
results of the ANDs are ORed together to produce bit 2. Bit 2 is ANDed with bit 3 and
when the result of this AND is 1, a VMEbus interrupt will be generated. The level of the
VMEbus interrupt is determined by the setting of Switch bank S2 (see Section 2.4.5).
Section 3.8 describes in detail how interrupts are generated.
3.6 INTERRUPT
ACKNOWLEDGE (IACK) VECTOR REGISTER
(base+83H)
This write-only register holds the vector to be driven on the VMEbus when a VMEbus
interrupt generated by the XVME-212 is acknowledged.
3.7 DATA REGISTERS
Four read-only Data Registers hold the state of the XVME-212’s four input ports (see
Figure 3-3).
3-8
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