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XVME-212 Manual

August, 1989

Signal
Mnemonic

IACK*

IRQI*
IRQ7*

LWORD*

(RESERV-
ED)

SERCLK

SERDAT

SYSCLK

Table B-l. VMEbus Signal Identification (cont’d)

Connector

and

Pin Number

1 A:20

1 B:24-30

lC:13

2B:3

lB:21

1 B:22

lA:10

Signal Name and Description

INTERRUPT ACKNOWLEDGE: Open-collector or three-
state driven signal from any master processing an interrupt

request. It is routed via the backplane to slot 1, where it
is looped-back to become slot 1 IACKIN in order to start
the interrupt acknowledge daisy-chain.

INTERRUPT REQUEST (l-7): Open-collector driven
signals,

generated by an interrupter, which carry

prioritized interrupt requests. Level seven is the highest

priority.

LONGWORD: Three-state driven signal indicates that the

current transfer is a 32-bit transfer.

RESERVED: Signal line reserved for future VMEbus
enhancements. This line must not be used.

A reserved signal which will be used as the clock for a
serial communication bus protocol which is still being
finalized.

A reserved signal which will be used as the transmission

line for serial communication bus messages.

SYSTEM CLOCK: A constant 16-MHz clock signal that is
independent of processor speed or timing. It is used for

general system timing use.

B-4

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Содержание XVME-212

Страница 1: ...utilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In stoc...

Страница 2: ...O 1997 XYCOM INC Digital Input Module PIN 74212 001B Printed in the United States of America Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 3: ...yrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information containedwithin this document is subject to change without...

Страница 4: ...Switches S2 2 8 IACK Enable Jumpers Jl J2 2 8 Debounce Period Jumpers 54 511 2 9 Installation 2 9 Installation Procedure 2 11 Digital Input Connections 2 11 Mechanical Switch Relay Operation 2 13 XVM...

Страница 5: ...Bank S1 Base Address Switches 2 5 VMEbus Chassis 2 10 XVME 212 1 0 Interface Block and its Possible 3 2 Locations in Short 1 0Address Space Extended Status and Status Control Registers 3 5 Data Regis...

Страница 6: ...TITLE Privilege Options Address Modifier Code Options Interrupt Level Switches S2 IACK Enable Jumpers Debounce Period Jumpers Input Connector Signal Definitions Identification Data LED Status PAGE Art...

Страница 7: ...other than the 12V may be applied to the inputs within the l0V 50V input range however some board modification will be necessary i e cutting the well identified and easily accessible PC traces to the...

Страница 8: ...amming of Xycom VMEbus 1 0 modules simple and consistent The following features apply to the operation of the XVME 212 Module address space The XVME 212 and all VMEbus modules are controlled by writin...

Страница 9: ...l I I 5OV DC max Logic 1 10 to 5OV DC Logic 0 0 to lV DC Typical threshold 3V DC Input Voltage Range XVME 212 2 65V DC max Logic 1 2 to 6 5V DC Logic 0 0 to 0 8V DC Typical threshold 1 2V DC 1 Input...

Страница 10: ...ng Extremely low humidity conditions may require special protection against static discharge Altitude Operating Non operating Vibration Operating Sea level to 20 000 ft 6096m Sea level to 50 000 ft 15...

Страница 11: ...andard l Al 6 D16 Data transfer bus slave l Base address jumper selectable within 64K short I O address space l Occupies 1K consecutive byte locations l I 1 to I 7 Interrupter STAT with programmable v...

Страница 12: ...nts for operation of the XVME 212 are one of the following either A or B below A A host processor properly installed on the same backplane A properly installed controller subsystem An example of such...

Страница 13: ...l August 1989 mmmm mmmm 1 I J4 J5 J6 J7 J8 J9 JIO JII L COMPONENT SIDE Figure 2 1 XVME 212 jumpers switches and connectors Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www...

Страница 14: ...elected by switches l 6 of the Address Switches Sl Privilege level required to access the module selected by Switch 7 of the Address Switches Sl VMEbus interrupt level selected by the Interrupt Level...

Страница 15: ...in J3 This jumper works in conjunction with Sl Switch 8 for address space selection i e Short I O Address Space or Standard Address Space See note below J4 Jll Determines the debounce period Note See...

Страница 16: ...shows the Switch bank S1 and how the individual switches 1 6 relate to the base address bits Figure 2 2 Switch Bank S1 Base Address Switches When a switch is in the closed position i e when it is pus...

Страница 17: ...NOOH 3400h 3800H 3c00h 4000H 4400H 4800H 4c00h MOOH 5400h 5800H 5c00h 6000H 6400H 6800H 6c00h 7000H 7400H 7800H 7c00h 8000H 8400h 8800H 8c00h 9000H 9400H 9800H 9c00h AOOOH A400H ASOOH ACOOH BOOOH MOO...

Страница 18: ...ard Address Space Note that in this mode the XVME 212 will always reside within the upper 64 Kbyte segment of the Standard Memory Address Space i e the address range FF0000H through FFFFFFH Sl switche...

Страница 19: ...S2 3 OPEN OPEN OPEN OPEN CLOSED CLOSED CLOSED S2 2 OPEN OPEN CLOSED CLOSED OPEN OPEN CLOSED S2 1 OPEN CLOSED OPEN CLOSED OPEN CLOSED OPEN VMEbus Interrupt Level 7 6 5 4 3 2 1 None interrupts disabled...

Страница 20: ...ation of time T the change will be reported to the scanner at the end of time period T This means that the input must assume the new state and stay in the new state without bouncing for time T before...

Страница 21: ...backplane connectors are depicted the P1 backplane and the P2 backplane However the XVME 212 uses only the P1 backplane PI BACKPLAN GUIDE SLOT SOLDER SIDE I N XP VME BOARD P2 BACKPLAN Figure 2 3 VMEb...

Страница 22: ...connector engage the board should slide freely in the plastic guides 4 Apply straightforward pressure to the handle on the panel front until the connector is fully engaged and properly seated NOTE It...

Страница 23: ...CH2 CH18 CH2 CH18 CH3 CH19 CH3 CH19 CH4 CH20 CH4 CH20 CH5 CH21 CH5 CH21 CH6 CH22 CH6 CH22 CH7 CH23 CH7 CH23 CH8 CH24 CH8 CH24 CH9 CH25 CH9 CH25 CHl0 CH26 CHlO CH26 CHIl CH27 CHll CH27 CH12 CH28 CH12 C...

Страница 24: ...ion applies onlv to channels which have their break point cut The 300V channel to VMEbus isolation is maintained whether the break points are cut or not because the 12V supply is isolated to 300V 2 7...

Страница 25: ...scribed in Section 2 4 1 located in the 64K Address space It this address space When located at its base address the XVME 212 is allotted a 1K block of address space for its own use This 1K block of a...

Страница 26: ...pt Ack Vector read only 7FH 81H readlwrite 83H write only Undefined Undefined 8BH read only 8DH 8FH I Data Register 0 Data Register 2 Change Register 0 Figure 3 1 XVME 212 110 Interface Block and its...

Страница 27: ...h hold the data from the four ports Change registers which indicate whether data on any channel has changed Note Reading or writing to undefined locations may make application software incompatible wi...

Страница 28: ...always XYC for XYCOM modules 3 characters Module Model Number 3 characters and 4 trailing blanks Number of IK byte blocks of 110 space occupied by this module 1 character Major functional revision lev...

Страница 29: ...und sequentially at locations 101lH 1013H 1015H 1017H 1019H IOlBH and 10lDH 3 5 EXTENDED STATUS base 80H and STATUS CONTROL REGISTERS base 81H Writing to the Status Control Register controls the red a...

Страница 30: ...test 2 Note The XVME 212 is a non intelligent module so all diagnostics must be performed by the system host VMEbus Interrupt Pendinq This read only bit reads 1 whenever BOTH of the following conditio...

Страница 31: ...t Writing a 1 in one of these bits enables interrupts from a specific Change Register writing 0 disables interrupts from the register Bit 4 Enables disables Change Register 0 Bit 5 Enables disables Ch...

Страница 32: ...rrupts Bits 4 7 of the Status Control Register are individually ANDed with bits 8 11 The results of the ANDs are ORed together to produce bit 2 Bit 2 is ANDed with bit 3 and when the result of this AN...

Страница 33: ...This is the only mechanism with the exception of VMEbus resets which will reset the Change Register bits Each Change Register bit will be set again when the input state is different from the image in...

Страница 34: ...bble four inputs at a time for state transitions Eight nibbles 32 input channels must be checked to complete one scan The architecture of the scanner does not allow it to be stopped in the middle of a...

Страница 35: ...the Status Control Register bits 4 7 When this bit is set a VMEbus interrupt will be generated when any bit of the corresponding Change Register is set and the VMEbus Interrupt Enable bit bit 3 of th...

Страница 36: ...t 7 33 Bit3 NOTE The numbered bits are located in the Extended Status and Status Control Registers base 080H See Figure 3 2 VMEbus Interrupt Figure 3 5 Generating a VMEbus Interrupt Artisan Technology...

Страница 37: ...rd 2 read Data Registers 0 and 1 as one word 3 read Change Registers 2 and 3 as one word 4 read Data Registers 2 and 3 as one word During the time that the scanner is stopped no changes in state will...

Страница 38: ...Channel Signals with Respect to Stopping the Scanner The Data and Change Registers contain the following data at the end of the designated scan After scan n n 1 n 2 n 3 Change Register read at point...

Страница 39: ...e Data or Change Registers directly It is not necessary to read the Change Registers at all if the user is not concerned about which individual bit in the change register is set In these cases the use...

Страница 40: ...determine the operational condition of specific modules within the system 4 Interrupt Control How software is able to control and monitor the capability of the module to interrupt the system 5 Commun...

Страница 41: ...ements Figure A 1 shows an abbreviated view of the short 1 0 memory short 1 1 0 Address Space Base Address Jumper Options Jumpers J8 57 J5 5 4 A13 A12 A l l AIO IN IN IN IN IN IN IN OUT IN IN OUT IN I...

Страница 42: ...ule holds specific I O status data and pointer registers for use with IPC protocol All intelligent XVME I O modules have an area of their I O Interface Blocks defined as dual access RAM This area of m...

Страница 43: ...nformation in an ASCII encodedi ormat The ITD data is provided as 32 ASCII encoded characters consisting of board type manufacturer identification module model number number of 1 Kbyte blocks occupied...

Страница 44: ...necessary to use odd backplane addresses to access the I D data Thus each of the 32 bytes of ASCII data has been assigned to the first 32 odd 1 0 Interface Block bytes odd bytes 1H 3FH The I D inform...

Страница 45: ...tates for the module test conditions on both the intelligent 1 0 modules and the non intelligent 1 0 modules Red LED 1 Green LED FRONT VIEW XXXX XVME XXX FAIL TEST w PASS Status Bits LEDs 3 2 1 0 Gree...

Страница 46: ...telligent XVME I O modules the status control register is used to indicate the state of the front panel LEDs and to set and verify module generated interrupts The LED status bits are Read Write locati...

Страница 47: ...Write Green LED 0 Green LED Off 1 Green LED On 2 Read Only Interrupt Pending 0 No Interrupt 1 Interrupt Pending 3 Read Write Interrupt Enable 0 Interrupts Not Enabled 1 Interrupts Enabled Bit Intellig...

Страница 48: ...a standard kernel combined with module dependent application circuitry Module standardization results in more efficient module design and allows the implementation of the Standard I O Architecture Th...

Страница 49: ...lector driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels are not being met INTERRUPT ACKNOWLEDGE IN Totem pole d...

Страница 50: ...driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector driven signal generated by a slave It indicates tha...

Страница 51: ...d transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data bus...

Страница 52: ...ignals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit tra...

Страница 53: ...system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indi...

Страница 54: ...system to be reset WRITE lA 14 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indic...

Страница 55: ...nemonic DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 GND SYSCLK G N P DSl DSO WRITE GND DTACK GI AS GND IACK IACKIN IACKOUT AM4 A07 A06 A05 A04 A03 A02 A0 1 12v 5v in Assignments Row B Signal Mnemonic BBSY BCLR AC...

Страница 56: ...Block Diagram CHANNELS CHANNELS I CONNECTORJK1 I I CONNECTOR JK2 I 1 OPTICALFLATOR 1 SCANNER c CHANGE REGISTERS DATA REGISTERS I VMEbus INTERFACE I V O STANDARD INTERFACEI Artisan Technology Group Qua...

Страница 57: ...XVME 212 Manual August 1989 Assembly Drawing JK2 I L 1 L I COMPONENT SIDE Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 58: ...1 1 r x N N N N N N N Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 59: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 60: ...STAT D 1 2 YRCTL D I I ERESET D 1 2 BUFENI D I 1 YRITEL D 1 1 DlTR BUS 5v 1I BUFFERS A 74LS645 1 Rev A XVME 212 DIN Schematic Sheet 3 of 7 Artisan Technology Group Quality Instrumentation Guaranteed 8...

Страница 61: ...N N N N N 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 62: ...NGZIEN D RSTINTI I CHRNGE DETECT I I INTEN 1LEVl BRl ILEVl on2 ILEVZ BR3 S I N 1 BDSl BOSO VRVEC HZ IPEN 3 LINT 3 DEBOUNCE CLOCK GENEROTOR IRCK VECTOR nYLEv 2 a OCLK 6 7 Rev A CLOCK DRIVER XVME 212 DI...

Страница 63: ...Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 64: ...W N Z Z l Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Страница 65: ...ule Identification Data Extended Status 8AH I Data Register 2 I Data Register 3 Status Control Undefined 8CH 8EH read only 83H write only Change Register 0 Change Register 2 8BH read only 8DH 8FH I Ch...

Страница 66: ...N OPEN CLOSED CLOSED CLOSED CLOSED S2 2 OPEN OPEN CLOSED CLOSED OPEN OPEN CLOSED CLOSED S2 1 OPEN CLOSED OPEN CLOSED OPEN CLOSED OPEN CLOSED VMEbus Interrupt Level 7 6 5 4 3 2 1 None interrupts disabl...

Страница 67: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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