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XVME-200/290 Manual
December, 1987

VMEbus Compliance

Complies with VMEbus Standard Rev. C.l
A 16:D8(0) DTB Slave
I(1) to I(7) interrupter (STAT) with
programmable interrupt vector

Size  - Single (XVME-200
Size  - Double (XVME-290)
Base address jumper-selectable on  1K
boundaries within the VMEbus short I/O
address space

l-8

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Содержание XVME 200

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Страница 5: ...h can be used to generate periodic interrupts a single interrupt after a specified time period or a square wave The specific features of the DIO Module are listed below Direct compatibility with OPT0...

Страница 6: ...erms of the backplane signal pin descriptions a block diagram and assembly drawing and module schematics NOTE In order to fully document the complex vers atility of the XVME 200 290 and the 68230 PI T...

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Страница 9: ...escription of Port Modes In addition any of the submodes within Port Modes 0 and 1 may be utilized There are 4 buffered handshake lines for each PI T chip which depending on the operation mode selecte...

Страница 10: ...XVME 200 290 Manual December 1987 1 4 MODULE SPECIFICATIONS The following is a list of the operational and environmental specifications for the XVME 200 290 DIO Module 1 6...

Страница 11: ...size 150 x 116 7 mm XVME 200 Double height size 160 x 233 4 mm XVME 290 Temperature Operating Non Operating Humidity Altitude Operating Non Operating Vibration Operating Non Operating Shock Operating...

Страница 12: ...mplies with VMEbus Standard Rev C l A 16 D8 0 DTB Slave I 1 to I 7 interrupter STAT with programmable interrupt vector Size Single XVME 200 Size Double XVME 290 Base address jumper selectable on 1K bo...

Страница 13: ...subsystem module which employs a Data Transfer Bus Arbiter a System Clock driver a System Reset driver and a Bus timeout module The XYCOM XVME 010 System Resource Module provides a controller subsyst...

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Страница 17: ...2 4 3 of this manual 2 4 1 Base Address Jumpers The DIO Module can be configured to be addressed at any one of the 64 IK boundaries within the VME Short I O Address space by using jumpers JAI0 throug...

Страница 18: ...N OUT OUT OUT OUT OUT I N IN I N I N OUT OUT OUT OUT I N I N IN I N OUT OUT OUT OUT IN IN I N I N OUT OUT OUT OUT IN I N IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT IN IN 2 6 I N OUT OUT I N I...

Страница 19: ...espond to This jumper is labeled as J2 see Figure 2 1 for the jumper location Jumper J2 determines whether the module will respond to supervisory or to non privileged short I O VMEbus cycles When jump...

Страница 20: ...e DIO Module and are hardwired together on the module to allow the Bus Arbitration Daisy Chain to pass through the backplane slot occupied by the DIO Module In each slot of the VMEbus backplane there...

Страница 21: ...n of pin H2 must be consistent with the position of the corresponding jumper J1 or J3 Table 2 5 shows the relationship between the position of jumpers Jl and J3 and the direction of the buffered hands...

Страница 22: ...ME 290 2 JKl carries signals for PI T l and JK2 carries signals for PI T 2 NOTE Connectors JKl and JK2 are directly compatible with OPT0 22 24 point subsystems flat cables can be con nected directly f...

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Страница 24: ...definitions and pin outs for the connector are found in Appendix A of this manual The Pl connector is designed to mechanically interface with a VMEbus defined Pl backplane 2 5 3 P2 Connector XVME 290...

Страница 25: ...12 PA6 1 P2A 13 PA4 1 P2B 13 v c c P2C 13 GND P2A 14 PA2 1 NO CONNECT P2C 14 PA3 1 P2A I 5 PAL1 NO CONNECT P2C 15 GND P2A 16 GND NO CONNECT P2C 16 PAO I P2A 17 H4 OUT 2 NO CONNECT P2C 17 GND P2A 18 T...

Страница 26: ...ll relevant jumper configurations and all connections to external devices or power supplies Please check the jumper configuration against the diagrams and lists in this manual To install a board in th...

Страница 27: ...XVME 200 290 Manual December 1987 5 Once the board is properly seated it should be secured to the chassis by tightening the two machine screws at the extreme top and bottom of the board 2 15...

Страница 28: ...VMEbus defined 64K short I O address space When the DIO Module is installed in the system it will occupy a 1K byte block of the short I O address space The base address decoding scheme for the XVME I...

Страница 29: ...7 3 49 Port C Data Direction Register 7 5 4B Port Interrupt Vector 7 7 4D Port A Control Register 79 4 F Port B Control Register 81 51 Port A Data Register 8 3 53 Port B Data Register 8 5 55 Port A A...

Страница 30: ...1041H NOTE The XVME 200 290 are an odd byte only slave and as such the module will not respond to even address single byte accesses However word accesses may be used with the understanding that only...

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Страница 32: ...ACK vector registers must be initialized before interrupts are enabled refer to 68230 Manual 3 3 1 Module VMEbus Interrupt Enabling As mentioned in the previous section the ports and timer of both PI...

Страница 33: ...be employed as a general purpose input line 3 is used as a timer output line if the 68230 timer function is being utilized If the timer function is not being used this bit could be employed as a gener...

Страница 34: ...and timer being generated 2 Write 1BH to the PORT C Direction register This will configure the direction of PORT C as shown in Figure 3 2 with the exception of pin 5 PIRQ which remains an input to en...

Страница 35: ...either as a simple timer output or as a general purpose PORT C output line 3 4 PI T PORT A AND PORT B DATA LINES The I O lines connected to the PI T I O pins are labeled PA0 PA7 and PB0 PB7 refer to...

Страница 36: ...ssume the same direction this direction must be consistent with PC0 as shown in Table 3 3 PI T pins PBO PB7 must all be programmed to assume the same direction this direction must be consistent with P...

Страница 37: ...PCDDR PIVR PACR PBCR PADR PBDR PAAR PBAR PCDR PSR TCR TIVR CPRH CPRM CPRL CNTRH CNTRM CNTRL TSR EQU 01 Port general control register EQU 03 Port service request register EQU 05 Port A data direction...

Страница 38: ...C bit 7 non latched input will always read as one 11 The handshake pins Hl H2 H3 H4 are at a low voltage level when negated and at a high voltage level when asserted 12 Hl is an edge sensitive status...

Страница 39: ...and B all bits double buffered outputs Port C bit 0 single buffered output controls the direction of the transceiver connected to Port A Port C bit 1 single buffered output controls the direction of t...

Страница 40: ...A0 3 M0VE B A6 TCR AO 9 H34 H12 interrupts enabled Timer setup PC3 TOUT TOUT function PC7 TIACK TIACK function Counter reloads on zero detect PC2 TIN TIN function Timer disabled A0 base address of PI...

Страница 41: ...M0VE B CHIGH CPRH AO Initialize counter preload registers M0VE B CMID CPRM AO M0VE B CLOW CPRL AO M0VE B TVCTR TIVR AO Initialize timer IACK vector BCLR 4 PCDR AO Set PC4 0 to enable timer interrupts...

Страница 42: ...lA 21 1A 22 1A 23 lB 16 17 18 19 lC 14 lA 18 Signal Name and Description AC FAILURE Open collectors driven signal which indicates that the AC input to the power supply is no longer being provided or...

Страница 43: ...ate that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector dr...

Страница 44: ...driven signal that indicates during byte and word transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byte and word trans...

Страница 45: ...in INTERRUPT REQUEST l 7 Open collector driven signals generated by an interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal ind...

Страница 46: ...ctor driven signal which when low will cause the system to be reset WRITE lA l4 WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high l...

Страница 47: ...A Row B Signal Signal Mnemonic Mnemonic DO0 BBSY D01 BCLR DO2 ACFAIL DO3 BGOIN DO4 BGOOUT DO5 BGlIN DO6 BGlOUT DO7 BG2IN GND BG20UT SYSCLK BG3IN GND BG3OUT DSl BRO DSO BRl WRITE BR2 GND BR3 DTACK AM0...

Страница 48: ...C 12 PA6 1 P2A 13 PA4 1 P2B 13 v c c P2C 13 GND P2A 14 PA2 1 NO CONNECT P2C 14 PA3 1 P2A 15 PAl 1 NO CONNECT P2C 15 GND P2A 16 GND NO CONNECT P2C 16 PAO 1 P2A 17 H4 OUT 2 NO CONNECT P2C 17 GND P2A 18...

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