Xycom XVME 200, Руководство пользователя

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XVME-200/290 Manual
December, 1987
M0VE.B #$AS,PBCR(AO)
M0VE.B #$18,PSRR(AO)
M0VE.B #O,PADDR(AO)
M0VE.B #$FF,PBDDR(AO)
BCLR
#O,PCDR(AO)
M0VE.B #O,TCR(AO)
; Initialize Port B
; Submode 1X
; H4 = asserted output
; H3 & H4 interrupts disabled
; PC4 = Port C function
; PCS/PIRQ = PIRQ function
; PC6/PIACK = PIACK function
; Set Port A & B direction
; Port A = input mode
; Port B = output mode
‘; Port A transceiver = input mode
; PC2, PC3 & PC7 = Port C function
; timer disabled
After
this initialization code is executed, PI/T #1 Port A data register will reflect
the state of PA7-1 through PAO-I. Data written to PI/T #I Port B will appear on
PB7-1 through PBO-I.
Example #2
Basic Set Up:
PI/T #2
Mode 1 = Unidirectional 16-bit Mode
Submode X l = Pin-Definable Double-Buffered Output or Non-Latched Input
Goals:
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
Port A and B, all bits = double buffered outputs.
Port C, bit 0 = single buffered output (controls the direction of the
transceiver connected to Port A).
Port C, bit 1 = single buffered output (controls the direction of the
transceiver connected to Port B).
Port C, bit 2 = TIN function.
The prescaler will not be used. The signal TIN
will be used to decrement the counter.
Port C, bit 3 = TOUT function.
Port C, bit 4 = single-buffered output (controls the timer interrupt enable).
Port C, bit 5 = PIRQ* function.
Port C, bit 6 = PIACK* function.
Port C, bit 7 = TIACK* function.
The handshake pins (Hl,H2,H3,H4) are at a low voltage level when negated,
and at a high voltage level when asserted.
Hl is an edge-sensitive input, HIS is set by an asserted edge of Hl, and Hl
interrupt is enabled.
H2 is an edge-sensitive input, and H2S is set by an asserted edge of H2, and
H2 interrupt is disabled.
H3 and H4 set up for interlocked output handshake protocol.
H4 interrupt is disabled.
Timer is set up to interrupt after timeout (and started).
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