Xycom XVME 200, Руководство пользователя

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XVME-200/290 Manual
December, 1987
Table 3-3 shows how pins
PC0
and PC1 affect the direction of the PORT A and B
data transceivers. Remember, each PI/T chip has its own PORT A and B, and thus
there is a total of 4 lines which are used to control the direction of the four data
transceivers (refer to the Module Block Diagram, Figure l-l).
Table 3-3. PORT A and B Data Transceiver Direction Control *
\
PC0
output
PC1 output
0
1
0
1
* These directions are the same for both PI/T chips.
Data Line Transceiver Direction
I
PA0-PA7 are OUTPUTS
PA0-PA7 are INPUTS
PB0-PB7 are OUTPUTS
PB0-PB7 are INPUTS
CAUTION
PI/T
pins PA0-PA7 must all be programmed to
assume the same direction, this direction must be
consistent with PC0 as shown in Table 3-3. PI/T
pins PBO-PB7 must all be programmed to assume the
same direction, this direction must be consistent with
PC1 as shown in Table 3-3. Failure to observe these
conventions will cause signal contention.
3.4.1
Port
A
and
B Reset
State
During a VMEbus reset, PI/T PORTS A, B, and C all assume an input direction.
Therefore, I/O signals PAO-PA7 and PBO-PB7 all assume an input direction during a
reset.
This means that if the I/O signals are being used in an application as
outputs, they will have a “high” reset state. Thus, active “low” outputs would have
to be used on lines which must be negated on power-up or system reset. The
receivers of these active “low” outputs should limit their value below 250uA to
guarantee that they will be negated upon reset.
3-9