MTi 1-series User Manual
Xsens MTi User Manual Repository
Datasheet
Copyright © 2021 Xsens
Page 24
Implemented I
2
C bus protocol features
Feature
Slave Requirement
MTi 1-series
7-bit slave address
Mandatory
Yes
10-bit slave
address
Optional
No
Acknowledge
Mandatory
Yes
Arbitration
N/A
N/A
Clock stretching
Optional
Yes
#4
Device ID
Optional
No
General Call
address
Optional
No
Software Reset
Optional
No
START byte
N/A
N/A
START condition
Mandatory
Yes
STOP condition
Mandatory
Yes
Synchronization
N/A
N/A
[4] The MTi-1 module relies on the I
2
C clock stretching feature to overcome fluctuations in
processing time. The Master is required to support this feature.
Writing to the MTi 1-s
Write operations consists of a single I
2
C write transfer. The Master addresses the module and
the first byte it sends is the opcode. The bytes that follow are the data bytes. The interpretation
of these data bytes depends on the opcode, as described in #MTSSP.
The maximum message size a module can receive is 512 bytes. If the Master sends more than
512 bytes, the module will reset its receive-buffer, which reduces the received message to
consist only of the excess bytes.
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